Kabushiki Kaisha Toshiba

Fujitsu Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

The Yokohama Rubber Co., Ltd.

Susumu Watanabe

Satoshi Tanaka

Mitsuhiro Yano

Toshiya Kotani

Sachiko Kobayashi

Sadakazu Takei

Osamu Ikenaga

Mayuko Morita

Masashi Wakatsuki

Sachiko Kobayasi

Hajime Hoashi

Toshiba Kotani

Hiroshi Takamure

A non-transitory computer-readable medium including a program, which when executed by a computer, causes the computer to execute a process including obtaining first information indicating a load in the computer, second information indicating a first amount of communication handled by a virtual switch executed in the computer, and third information indicating a second amount of communication between the computer and another computer; and determining whether to switch from a first mode, in which the virtual machine executes a switch operation, to a second mode, in which the virtual switch and a physical switch that relays a communication of the computer cooperatively execute the switch operation, on the basis of the first information, the second information and the third information.

Computer-readable medium, apparatus, and method for offloading processing from a virtual switch to a physical switch

An information processing apparatus includes a versatile Operating System (OS) that performs a time measurement process in response to a request from an application, a storage unit that stores a process load of the versatile OS and a delay time of the time measurement process in combination, a detecting unit that detects a process load of the versatile OS when the application requests the time measurement process, an acquiring unit that acquires a delay time that corresponds to the process load, which is detected by the detecting unit, as an expected delay time from the storage unit, and a requesting unit that requests the versatile OS to measure a requested measurement time that is obtained by subtracting the expected delay time, which is acquired by the acquiring unit, from a measurement time that is requested by the application.

Information processing apparatus and time measurement method

A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Manufacturing method of semiconductor device

Pattern correction method of semiconductor device

An integrated circuit design method and an integrated circuit design apparatus, for increasing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing the data in parallel, take a first construction of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells, then creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group, and take a second construction of restoring a non-overlapped array data region left by excluding a data region having overlapped data from an array data region containing array data among pieces of integrated circuit design layout data, with a combination of a plurality of or a single piece of array cell or unit cell.

Method of designing integrated circuit and apparatus for designing integrated circuit

A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.

Mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus

A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.

Pattern data generation system, method and program for pattern data generation, reticle fabricating method, and semiconductor device manufacturing method using the pattern data

Automobile tire

An LSI mask writing data compressing system and method according to the present invention generates first-coordinate-axial one-dimensional arrays for each individual layout pattern, each of which comprises individual layout patterns having the same shape repeatedly arranged at regular intervals in the direction of a first coordinate axis, second-coordinate-axial one-dimensional arrays for each individual layout pattern, each of which comprises individual layout patterns having the same shape repeatedly arranged at regular intervals in the direction of a second coordinate axis perpendicular to the first coordinate axis, two-dimensional arrays for each individual layout pattern, each of which comprises first-coordinate-axial one-dimensional arrays for each individual layout pattern repeatedly arranged at regular intervals in the direction of the second coordinate direction, a first-coordinate-axial block array of multiple layout patterns, which comprises grouped first-coordinate-axial one-dimensional arrays for each individual layout pattern, which include the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of the first coordinate axis, a second-coordinate-axial block array of multiple layout patterns, which comprises grouped second-coordinate-axial one-dimensional arrays for each individual layout pattern, which include the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of the second coordinate axis, and a two-dimensional block array of multiple layout patterns, which comprises grouped two-dimensional arrays of individual layout patterns, which include the same number of individual layout patterns repeatedly arranged at the same regular intervals, to convert data for each of the arrays to prepare writing data for a hierarchical cell.

System and method for compressing LSI mask writing data

There is disclosed a specific method, which is applied to a charged particle beam pattern drawing system, for drawing a circuit pattern on a workpiece using a charged particle beam. A circuit pattern to be drawn is first divided into unit figures by parallel line segments extending from the vertexes of the figure that has a polygonal planar shape in a first reference direction. Each of the unit figures corresponds to a specific reference figure registered in advance. When the divided unit figures include an elongated too-small figure having at least one side shorter than a predetermined minimum allowable length, the too-small figure is merged with at least one unit figure adjacent to it at least once, and thus an expanded unit figure is defined. The expanded unit figure is divided into new unit figures by parallel line segments extending from its vertexes in a second reference direction perpendicular to the first reference direction so as to correspond to the reference figures. As a result, remaining of the too-small figures in the circuit pattern to be actually subjected to charged particle beam pattern drawing is minimized.

Method for drawing a desired circuit pattern using charged particle beam

Dot pattern data stored in the first dot pattern memory is read out by a predetermined number of successive bits at a time under the control of a microprocessor and corrected with respect to an X direction. The corrected dot pattern data is temporarily stored in a main memory. The dot pattern data stored in the main memory is then corrected with respect to a Y direction. The resultant corrected dot pattern data is stored in a second dot pattern memory for use for electron beam blanking control.

Growing community of inventors

Kanagawa-ken, Japan

Susumu Watanabe