Hitachi, Ltd.

Susumu Tsuruta

Daisuke Isobe

Hideaki Fukuda

Masanori Takada

Tomohiro Yoshihara

Makio Mizuno

Koji Akiyama

Shoji Kato

Masateru Hemmi

Suguru Shimotaya

Hiroshi Shimmura

It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.

Storage system and data transfer control method

According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.

Storage system and method for prioritizing data transfer access

It is an object to prevent a processing speed of the storage system provided with a function for detecting a write completion of data from being reduced. A controller module is provided with at least one processor module, at least one storage resource, and at least one transfer control module connected to the processor module and the storage resource. The transfer control module is provided with a receiver and a transmitter. The receiver receives a write packet from the processor module, includes a specific code in the write packet, and then transmits the write packet. In the case in which the transmitter receives a write packet and the received write packet includes the specific code, the transmitter writes targeted data in the write packet to the storage resource to be written, generates a response packet that is a response indicating a completion of a write, and transmits the generated response packet.

Storage system provided with function for detecting write completion

A data transfer controller of the present invention can determine whether or not data has been correctly stored in a cache memory even when the data is not transferred to the cache memory in sequential order. Data inputted from a host is transferred to and stored in a prescribed area of the cache memory. First check data is created and stored for each block. A data consistency determination module reads out the data from the cache memory subsequent to the end of a data write, and creates second check data anew. By comparing the second check data against the first check data, it can be determined whether or not the data has been stored normally in the cache memory. The data consistency determination module can also determine the consistency of the data on the basis of the data address written to the cache memory.

Data transfer controller, data consistency determination method and storage controller

A storage control apparatus capable of reducing a power consumption in network port units, including a host communication control unitwhich includes a plurality of network portsand which controls communications with a host computerthat is connectable through the network ports, a storage-device communication control unitwhich controls communications with a plurality of storage devices, a plurality of DMA portionsby which data to be transmitted/received between the host computer and the storage devices are transferred between the host communication control unitand the storage-device communication control unit, a plurality of cache memoriesin which the data to be transferred by the DMA portionsare temporarily stored, and a power saving control portionwhich stops the DMA portionand the cache memorythat are previously associated with one network port, on the basis of a connection situation of the pertinent network port with the host computer and a data rate to be inputted/outputted to/from the pertinent port.

Storage control apparatus having power saving controller which stops particular data transfers based on connection and data transfer rates

An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

Interrupt control system and storage control system using the same

A storage control device provided with a plurality of channel control sections for receiving data input and output requests from an information processing device and transmitting and receiving data, to and from an information processing device, each of the plurality of channel control sections comprising: an input/output control section for receiving data input and output requests from the information processing device and controlling transmission and reception of data between a data storage memory and the information processing device; a processor; a data storage memory; and a data transfer device for transferring data in the data storage memory to a cache memory; and in a first channel control section of the plurality of channel control sections, the processor manages the data storage space in the data storage memory, and in a second channel control section, the input/output control section manages the data storage space in the data storage memory, and reports information relating to the data storage space to the processor.

Growing community of inventors

Odawara, Japan

Susumu Tsuruta