Nec Corporation

Nec Electronics Corporation

Nippon Electric Co., Ltd.

Epson Toyocom Corporation

Susumu Kurosawa

Yasutaka Nakashiba

Yoshinori Muramatsu

Yuki Fujimoto

Kouichi Kumagai

Tsuyoshi Nagata

Koichiro Okumura

Masayuki Ishikawa

Hiroaki Ohkubo

Hiroaki Iwaki

Tsuyoshi Ohshima

Shunichi Suzuki

Shigehisa Kurogo

Kazuo Terada

Deterioration in frequency stability with time in a conventional piezoelectric oscillator using an accumulation type MOS capacitance element is improved. A P-channel transistor type or an N-channel transistor type is used as a MOS capacitance element in a variable capacitance circuit used in a piezoelectric oscillator. A bias voltage is applied between P-type or N-type extraction electrodes formed in source and drain regions and an N-type extraction electrode provided in an N-well region or a P-type extraction electrode provided in a P-well region. Instability in the MOS capacitance element with time is thus eliminated.

Piezoelectric-oscillator

An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two pdiffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the pdiffusion regions are connected to a ground potential wiring. Further, an ndiffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two pdiffusion regions absorb positive holes serving as minority carriers from a channel region.

Voltage-controlled capacitive element and semiconductor integrated circuit

A P type substrate is provided on a surface thereof with varactor elements. The varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film is formed on the N well, with a polysilicon layer formed further thereon. On the other hand, the varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film, greater than the gate insulating film in thickness, is formed on the N well. The polysilicon layer is then formed on the gate insulating film. Furthermore, the polysilicon layer is connected to a gate terminal, while the N well is connected to an S/D terminal via Ndiffusion layers.

Voltage controlled variable capacitance device

First and second varactors are disposed on a surface of a P-type substrate. The first varactor includes an N well disposed in the surface of the P-type substrate, a gate insulator disposed on the N well, and an N-type polysilicon layer disposed on the gate insulator. The second varactor includes an N well disposed in the surface of the P-type substrate, a gate insulator disposed on the N well, and a P-type polysilicon layer disposed on the gate insulator. The N-type polysilicon layer and P-type polysilicon layer are connected to a gate terminal. The N wells are connected to an SD terminal via Pdiffusion layers. The N-type polysilicon layer and P-type polysilicon layer have different work functions.

Voltage-controlled variable-capacitance device

According to an image sensor disclosed, a pixel circuit includes a photo-diode for generating a photo-electric conversion voltage which corresponds to an input optical level, a transistor which is activated in response to a Reset signal RST, to initialize the photo-diode from a power supply VDD, a transistor which, when connected between the power supply VDD and a bit line BL, amplifies a photo-electric conversion voltage and outputs it onto the bit line BL, and a transistor which is activated by a word-line readout control signal WL, to interconnect the transistor and the bit line BL, in which the transistor is of a depletion type.

Image sensor

There is disclosed an image sensor wherein the dispersion in threshold voltages of a transistor constituting a source follower for outputting a signal is compensated. The disclosed image sensor is provided with a coupling capacitor to which an output voltage of a pixel is applied through a transistor and with a transistor of a source follower to read out a voltage at the node S/Hn of the coupling capacitor. The image sensor is so configured that a drain of a transistor is used as a power supply voltage and the transistor is turned on, causing a node S/Hn pre-charged to the power supply voltage, and then the transistor is turned on, causing the voltage of the node S/Hn to be clamped on a sum of a definite voltage and a threshold voltage of the transistor, and further the transistor is turned on, causing an output voltage generated when a pixel is exposed to light to be added to the capacitor, and by restoring the transistor to a power supply voltage of the drain and by again turning the transistor on, an output voltage generated when a pixel is unexposed to light is applied to the capacitor.

Image sensor for offsetting threshold voltage of a transistor in a source follower

There is disclosed a black-level signal generation circuit for use with a CMOS-based active pixel image sensor. This black-level signal generation circuit delivers a black-level signal of a constant level at all times. The black-level signal generation circuit is equivalent in circuit configuration to any one of pixels forming an effective pixel array and any one of readout portions for reading out signals from the pixels. A photodiode is maintained in a reset state. MOS transistors whose corresponding MOS transistors are turned 'ON/OFF' in any one of the pixels and any one of the readout portions are all kept in 'ON' state. Thus, the black-level signal generation circuit can constantly produce a black-level signal equivalent in level to the pixel signal delivered when no light is incident on the effective pixels.

MOS-based image sensor and method of forming black-level signal therefor

The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode in the first exposure period in pixel interior capacitance that is provided inside pixels and integrates the signal charge that is generated in photodiode in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side. In addition, the control signals are very few, and a fine timing control for changing over the mode is no longer required.

Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude

In a semiconductor integrated circuit, a control transistor,and a potential clamp circuit,are arranged between a power supply line,and a virtual power supply line,. Even in a sleeve mode where the control transistor,is turned off, the potential clamp circuit,-,clamps the virtual power supply line,at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor,can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.

Semiconductor integrated circuit device with low power consumption and simple manufacturing steps

In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode. A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode.

SOI-type semiconductor device with variable threshold voltages

A driver circuit comprising (i) a pair of complementary MOS (CMOS) transistors connected in series and receiving an identical input signal, and (ii) a pair of control transistors changing a threshold voltage state of each of the pair of CMOS transistors by applying a plurality of voltages to a body terminal of each of the pair of CMOS transistors depending upon the ON/OFF state of each of the pair of CMOS transistors. Such a driver circuit is capable of reconciling a high-speed operation with a low power consumption under low power supply voltage conditions.

Driver circuit

A library group structured of logic gates and function blocks which allow all of the requirements of high speed operation, low power consumption, and high integration to be satisfied and a load driving capability to be optimally selected without need to rework and modify the placement and wiring design work is provided. A library group is structured of basic cells of transistors with a small channel width and has plural logic gates and plural function blocks which have the same logic function, the same size, and the same input/output terminal positions and which have different load driving capability. A portion which performs a logical function is separated from a portion which performs a load driving function. The portion which performs the load driving function is structured of a lateral type bipolar device or a hybrid mode device corresponding to SOI technology.

Library group and semiconductor integrated circuit structured thereof

A new memory device of single transistor type is disclosed. A substrate has a surface portion of low impurity concentration and an inner portion of high impurity concentration, and a trench is formed in the substrate from the surface portion into the inner portion such that the trench surrounds a cell section of the substrate. A switching transistor is formed in the surface portion at the cell section, and a capacitor is formed in the trench such that a MOS type capacitor is constituted by a capacitor electrode, the lower side wall by the inner portion of the substrate and an insulating film therebetween. A bit line is connected to a conductive layer provided at the upper part of the trench, and the conductive layer is connected to the source or drain region of the transistor.

Growing community of inventors

Tokyo, Japan

Susumu Kurosawa