Kabushiki Kaisha Toshiba

Susumu Komatsu

Tatsuya Ishikawa

Noboru Taga

Masaki Nishikawa

Noriya Sakamoto

Satoyuki Ishii

An A/D conversion processing circuit includes: a switch sequentially switching over multiple inputs to select each thereof according to input bandwidth of the multiple inputs or fixedly selecting a single input; an A/D converter obtaining a digital signal through sampling on a switch output with a sampling frequency according to a necessary signal bandwidth; an interpolation section performing on each signal from a separation section which separates signals included in an A/D converter output, an interpolation processing according to a sampling timing deviation in the A/D converter, to obtain a signal where the multiple inputs are digitally converted at the same sampling timing; and an output section outputting as-is an output of the A/D converter if a signal of the single input is inputted to the A/D converter from the switch, thereby allowing commonly using a single A/D converter for multiple inputs, restraining increased circuit scale and power consumption.

Circuit and method for A/D conversion processing and demodulation device

AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal, and valid frequency error extractor for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.

AFC circuit for QPSK demodulator

A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.

Digital phase-locked loop circuit

A vertical edge detection circuit for a progressive scanning conversion circuit including an input circuit for receiving an interlaced scanning television signal, a first circuit for generating an intra-field difference signal from the interlaced scanning television signal, a second circuit for generating an inter-field difference signal from the interlaced scanning television signal and a third circuit for selectively outputting a maximum value one of the intra-field and inter-field difference signals.

Vertical edge detection circuit for a television image motion adaptive

An address control circuit for a video memory of a multi-image display system. The circuit includes a video signal source, a video memory for storing the video signal, an address holding circuit for controlling write addresses of the video memory which outputs address values during a video image period and holds address value corresponding to a start instance of a blanking period during the blanking period and a bias generating circuit for positioning address areas of the video memory in which the video signal is stored.

Growing community of inventors

Kanagawa, Japan

Susumu Komatsu