Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Holdings Co., Ltd.

Fuji Electric Systems Co. Ltd.

Shin-etsu Handotai Co., Ltd.

Susumu Iwamoto

Tatsuhiko Fujihira

Yasuhiko Onishi

Takahiro Sato

Katsunori Ueno

Tatsuji Nagaoka

Kouta Takahashi

Yasushi Miyasaka

Kenji Kunihara

Daisuke Kishimoto

Yasuhiko Ohnishi

Takashi Kobayashi

Seiki Igarashi

Satoshi Oka

Naotaka Matsuda

Hideaki Kakiki

Shunta Horie

Ryohsuke Shimizu

A semiconductor module, including a semiconductor chip that includes a switching device having a control electrode, and a control terminal connected to the control electrode, a first resistance being formed between the control electrode and the control terminal and having a positive temperature coefficient, and a second resistance connected to the control terminal, the second resistance having a negative temperature coefficient. A temperature coefficient of a combined resistance at the control terminal is zero or negative.

Semiconductor module

The semiconductor device includes a substrate having a main surface, a plurality of conductive patterns provided on the main surface, a plurality of switching elements disposed on one of the conductive patterns, each switching element having a first electrode and a second electrode and being connected to the one of the conductive patterns through its first or second electrode, and at least one first wiring member each directly connecting the first electrodes of two switching elements that are respectively disposed on different conductive patterns and are electrically connected in parallel.

Semiconductor device

A semiconductor device of the present invention suppresses high frequency noise caused in a semiconductor device incorporating SiC elements. The semiconductor device includes semiconductor elements connected in series, a SiC diode element connected in parallel to the semiconductor element, and an oscillation suppressing circuit being connected in parallel to the semiconductor element and the SiC diode element and suppressing voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element. The oscillation suppressing circuit suppresses voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element thereby improving reliability of the semiconductor device.

Semiconductor device and oscillation suppressing device

A space having a certain thickness is provided between a metal base and a heat-dissipation fin set or the like. A semiconductor device is provided, including: a package portion; a metal base which is housed in the package portion and is exposed at a lower surface of the package portion; a semiconductor chip which is housed in the package portion and is placed above the metal base; and a frame portion provided to surround a penetration space penetrating the package portion, wherein a lower end of the frame portion protrudes below the lower surface of the package portion and a lower surface of the metal base. It is preferable that the frame portion is inserted in the penetration space after the penetration space is formed in the package portion.

Semiconductor device and manufacturing method of semiconductor device

An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.

Semiconductor device and method of manufacturing the semiconductor device

A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field limiting rings. Each of the field plates project over a surface of each of the insulation films between the first field limiting rings and the second field limiting rings.

Semiconductor device and method of manufacturing same

A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region. The superjunction structure eliminates the lower limit that prevents further narrowing of the widths of the n-type and p-type regions to further improve the tradeoff relationship between increasing the breakdown voltage and reducing the on-resistance.

Semiconductor superjunction device

Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

Super-junction semiconductor device and method of manufacturing the same

A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.

Fabrication method of semiconductor wafer

A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

Lateral super-junction semiconductor device

A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions U. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions U, with the conductivity type thereof unchanged. The alternating-conductivity-type drain drift layer is formed by repeating the step of epitaxial layer growth and the step of implanting p-type impurity ions and by diffusing the impurity ions at once from the impurity sources located on multiple levels.

Growing community of inventors

Nagano, Japan

Susumu Iwamoto