Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Susumu Iesaka

Michiaki Hiyoshi

Hideo Matsuda

Takashi Fujiwara

Satoshi Yanagisawa

Shigenori Yakushiji

Hisashi Suzuki

Shigenori Yakushizi

Tatuo Harada

A reverse conducting gate-turnoff thyristor includes a switching device section, a diode section, and an isolating section located between the switching device section and the diode section. The isolating section includes an impurity layer formed by controlling impurity diffusion and having an impurity concentration lower than those of the switching device section and the diode section.

Reverse conducting gate-turnoff thyristor

A crimp-type semiconductor device is provided with a semiconductor substrate having a lifetime-controlled region. This lifetime-controlled region is in the form of a ring, and the lifetime of the minority carriers is shortened in the region. Second-conductivity type impurity regions, which serve as emitter layers, are formed on the semiconductor substrate such that they provide a plurality of concentric arrays. The inner diameter of the ring-like lifetime-controlled region is longer than the diameter of an enveloping circle which is obtained by connecting the radially-inner ends of the impurity regions of the outermost array.

Crimp-type power semiconductor device

A guard-ring-equipped Schottky barrier diode, which has a shortened reverse recovery time and an increased withstand voltage, has a Schottky barrier layer formed on a semiconductor substrate, of a first conductivity type, and a guard ring, which has a second conductivity type, formed on surface of the substrate isolated from but surrounding the periphery of the barrier layer. An insulative film with an opening over part of the guard ring is formed over the region between the edge of the Schottky barrier layer and the guard ring. A high-resistance layer is formed in this opening and is connected with the Schottky barrier layer by a metal electrode. The width of the substrate between the guard ring and the edge of the barrier layer is less than the sum of the widths of the depletion layers of the guard ring and the barrier layer at the time when the lower voltage of either the barrier layer breakdown voltage or the guard ring breakdown voltage is applied.

Schottky barrier diode with guard ring

A low-loss P-i-n diode includes an i-type layer consisting of first and second i-type regions formed on the cathode layer of the diode and the i-type has a thickness W.sub.i of less than 25 .mu.m. The impurity concentration of the first i-type region is higher than that of the second i-type region. To obtain a good forward-voltage V.sub.f, W.sub.i.sup.2 /.tau. is selected to be in the range of 20-200cm.sup.cm.sup.2/sec and the carrier lifetime .tau. of the i-type layer is controlled by a carrier lifetime killer with a small resistivity compensation effect which is diffused into the i-type layer. The P-i-n diode has a high reverse breakdown voltage, small forward-voltage drop and a short recovery time.

Low-loss P-i-n diode

A method of manufacturing a glass passivation semiconductor device by depositing a glass passivation layer on the surface of a semiconductor junction formed on a semiconductor substrate. First laser beams which can be substantially absorbed in the glass protective material and second laser beams which can be absorbed in the semiconductor substrate are simultaneously irradiated on those portions of the semiconductor substrate on which the glass protective material is deposited, thereby providing a glass passivation layer.

Method of manufacturing a glass passivation semiconductor device

A semiconductor device including at least first and second transistors having their respective emitter regions of a first conductivity type formed in a common base layer of a second conductivity type, the semiconductor device comprising a first electrode formed on the emitter region of the first transistor, the first electrode extending on that portion of the base layer which surrounds the emitter region of the second transistor, a second electrode formed on the base layer at the opposite side of the emitter region of the first transistor to that side of the base layer where the second transistor is formed, a first semiconductor region formed in the emitter region of the second transistor, the first semiconductor region having the second conductivity type and extending from the major surface of the emitter region of the second transistor to the base layer, an insulation film formed on the first semiconductor region, a portion of the first semiconductor region being left uncovered with the insulation film, a second semiconductor region formed in the first semiconductor region, the second semiconductor region having the first conductivity type and extending from the surface of the emitter region of the second transistor to the base layer, and a third electrode formed on the emitter region of the second transistor and the first semiconductor region.

Growing community of inventors

Tokyo, Japan

Susumu Iesaka