Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Elpida Memory, Inc.

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Ps4 Luxco S.a.r.l.

Susumu Hatano

Kunio Uchiyama

Toshio Sugano

Hideki Osaka

Kanji Oishi

Hirokazu Aoki

Toyohiko Komatsu

Kazuya Ito

Takashi Kikuchi

Hiroshi Fukuta

Yasuhiko Saigou

Koichi Kimura

Masachika Masuda

Takashi Tsunehiro

Osamu Nishii

Akihiko Iwaya

Yutaka Kagaya

Masashi Horiguchi

Yoji Nishio

Atsushi Oohashi

Katsuyuki Sato

Tadahiko Nishimukai

Yoshihiro Harada

Kensaku Kuroki

Jun Kitano

Yutaka Uematsu

Seiji Funaba

Takeshi Wada

Tsutomu Hara

Masashi Kawamura

Yasushi Takahashi

Yoji Idei

Masayasu Kawamura

Shin'ichi Ikenaga

Fujio Yamamoto

Haruki Nagahashi

Tadaaki Yoshimura

Kenji Nishimoto

Takao Hirayama

Michihiro Mishima

Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.

Semiconductor module includes semiconductor chip initialized by reset signal

A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Semiconductor memory device having input first-stage circuit

A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.

Data transmission device, data transfer system and method

A method of manufacturing a stator core for a dynamo-electric machine by preparing a cylindrical laminated body by winding into a helical shape a continuous first sheet formed by press-punching from a strip-shaped first magnetic steel sheet material, preparing a plurality of second sheets by press-punching from a thicker second magnetic steel sheet material, bending the second sheets into an annular shape and stacking the second sheets bent into the annular shape on both axial ends of the laminated body and integrating the stacked sheets by laser welding.

Method for manufacturing a stator core for a dynamoelectric machine

A method of manufacturing a stator core for a dynamo-electric machine, by preparing a cylindrical laminated body by winding into a helical shape a continuous first sheet formed by press-punching from a first magnetic steel sheet material. Preparing a plurality of second sheets having a predetermined length by press-punching from a thicker second magnetic steel sheet material. Next, chamfered portions are formed on edge portions of second recess portions by chamfering the second sheet. Then, the second sheets are bent into an annular shape and the second sheets bent into the annular shape are stacked on both axial ends of the laminated body and integrated by laser welding.

A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.

Memory system

A memory module bus system using a plurality of directional couplers to permit high-density packaging. A wiring line (main line) extending from a main controller and cooperating with a sub coupling line to form a directional coupler is open-ended or short-circuited to ensure that a forward wave and a reflection wave can be used to generate signals in opposite directions of the directional coupler. Memory modules are connected to opposite ends of the sub coupling line. The line length of the coupler can be half the pitch between the memory modules.

Data transmission system of directional coupling type using forward wave and reflection wave

A bus system for carrying out data transfer between one bus master and a plurality of bus slaves. The bus system includes plural directional couplers which are formed by arranging respective parts of lines drawn from the bus slaves, without being in contact with, in the neighborhood of, and in parallel with a line drawn from the bus master. The line drawn from the bus master to a terminating resistance is wired to be folded. The directional couplers are further formed by arranging parts of the lines drawn from the bus slaves alternatively with respect to a first line part of the line drawn from the bus master ranging from the bus master to a fold of the line drawn from the bus master and with respect to a second line part of the line drawn from the bus master ranging from the fold to the terminating resistance.

Bus system, memory system, printed circuit board and directional coupler

Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Directional coupling memory module

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate and control-use pads of control signals that are also placed on the center side of the substrate The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate

Semiconductor device

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate . Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate , and control-use pads of control signals that are also placed on the center side of the substrate . The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate

Surface mount-type package of ball grid array with multi-chip mounting

Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

Semiconductor memory device

Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

Multiprocessor cache system having three states for generating

Growing community of inventors

Higashimurayama, Japan

Susumu Hatano