Silicon Laboratories Inc.

Keyeye Communications

Susumu Hara

Zhuo Fu

Adam B Eldredge

Jeffrey S Batchelor

Jeffrey Lee Sonntag

Hiroshi Takatori

Yunteng Huang

Xue-Mei Gong

James Little

Daniel Gallant

James E Wilson

Adam D Eldredge

A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Cascaded PLL for reducing low-frequency drift in holdover mode

A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.

Interpolative divider linearity enhancement techniques

An apparatus includes a first conductive loop coupled to conduct a first current and a second conductive loop coupled in parallel with the first conductive loop and further coupled to conduct a second current. A first conductive portion forms a part of the first conductive loop and the second conductive loop. The first conductive portion is coupled to conduct the first current and the second current. In at least one embodiment of the apparatus, the first conductive loop and the second conductive loop are planar inductors formed in a conductive layer on a substrate of an integrated circuit.

Mutual inductance circuits

One or more PLLs are formed on an integrated circuit. Each PLL includes an interpolative divider configured as a digitally controlled oscillator, which receives a reference clock signal and supplies an output signal divided according to a divide ratio. A feedback divider is coupled to the output signal of the interpolative divider and supplies a divided output signal as a feedback signal. A phase detector receives the feedback signal and a clock signal to which the PLL locks. The phase detector supplies a phase error corresponding to a difference between the clock signal and the feedback signal and the divide ratio is adjusted according to the phase error.

PLL using interpolative divider as digitally controlled oscillator

An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter.

Oscillator with external voltage control and interpolative divider in the output path

A voltage control signal at a voltage control signal input terminal is used to adjust an output frequency of an oscillator circuit. The voltage level of the voltage control signal is converted in a one-bit analog-to-digital converter (ADC) to a digital output indicative of the voltage level. Successive digital representations of the voltage level of the voltage control signal are upsampled to generate upsampled blocks of data. A dither circuit inserts a digital dither in the upsampled blocks of data to generate dithered upsampled data, which is used to generate a control signal for a feedback divider of a phase-locked loop circuit and thereby adjust the output frequency.

Voltage controlled oscillator with dither

A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Fractional divider

Techniques for use with a fuse-based non-volatile memory circuit include digitally controlling a resistance threshold of the circuit. The circuit includes a fuse circuit and a comparator circuit. The comparator circuit is configured to compare a first signal indicative of the fuse resistance to a second signal indicative of a reference level. At least one of the first and second signals is digitally controllable. The comparator circuit is configured to generate a digital output signal indicative of the comparison. The circuit may include a first digital-to-analog converter circuit configured to generate a first analog signal based on at least a first plurality of digital signals. The first signal is at least partially based on the first analog signal. The circuit may include a control circuit configured to digitally control the digitally controllable ones of the first and second signals at least partially based on the digital output signal.

Variable sense level for fuse-based non-volatile memory

In one embodiment, the present invention includes an apparatus having a first amplifier stage to receive an input voltage and to provide an amplified output voltage at an output terminal, where the first amplifier stage is controlled by a first bias current. The apparatus may further include a second amplifier stage coupled to receive a control voltage and to provide an offset voltage to the output terminal, where the second amplifier stage is controlled by a second bias current. The first and second bias currents may be controlled by a single bias controller.

Signal dependent biasing scheme for an amplifier

A finite impulse response filter having tap weight rotation is provided, where each tap has a corresponding coefficient selector. Each coefficient selector includes N coefficients, where N is the number of taps. Each coefficient selector provides one of its corresponding coefficients as an input to a multiplier. Each multiplier also receives an input from a triggered track and hold tap. The tap coefficients are selected according to the time delay since the corresponding track and hold tap was most recently triggered. In this manner, the tendency of multiplier gain nonuniformity to degrade filter operation in the presence of tap weight rotation is reduced. In another embodiment, an offset selector is provided, to reduce the tendency of component offsets to degrade filter operation in the presence of tap weight rotation.

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Austin, TX, United States of America

Susumu Hara