Imec Vzw

Katholieke Universiteit Leuven

Katholieke Universiteit Leuven, Ku Leuven R&d

Vrije Universiteit Brussel

Sushil Sakhare

Trong Huynh Bao

Manu Komalan Perumkunnil

Mohit Gupta

Johan Swerts

Gouri Sankar Kar

Wim Dehaene

Pieter Weckx

Kevin Garello

Bharani Chakravarthy Chava

A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.

Multibit neural network

According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

Spin-torque transfer switchable magnetic tunnel junction unit and a memory device

A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

Circuit cell for a memory device or logic device

The disclosed technology relates generally to magnetic random access memory, and more particularly to spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM). According to an aspect, a MRAM device comprises a first transistor, a second transistor, and a resistive memory element. The resistive memory element comprises a magnetic tunnel junction (MTJ) pillar arranged between a top electrode and bottom electrode having a first terminal and a second terminal. According to another aspect, a method of using the MRAM device is disclosed.

Spin orbit torque magnetoresistive random access memory device

A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.

Non-volatile SRAM cell using resistive memory elements

The disclosed technology generally relates to memory devices and more particularly to memory devices based on resistance change, and to systems and methods for evaluating states of memory cells of the memory devices. In one aspect, a memory device includes a plurality of memory cells arranged in an array, where each memory cell comprises a memory element configured to be switched between at least two resistance states. The memory device additionally includes a plurality of word lines and a plurality of bit lines crossing each other, where each of the memory cells is formed at a crossing between one of the word lines and one of the bit lines. In the memory device, the memory cells are configured to be connected to a source line. Additionally, each bit line has a bit line capacitance and is configured to store a charge associated with a state of a selected memory element. Additionally, at least two memory cells electrically connected between one of the word lines and at least two different bit lines are configured as reference cells, where one of the reference cells is in a high resistance state and the other of the reference cells is in a low resistance state. Furthermore, the at least two different bit lines electrically connected to the reference cells are interconnected by an equalizing switch configured to equalize charges associated with bit line capacitances of the at least two bit lines.

Growing community of inventors

Heverlee, Belgium

Sushil Sakhare