Oracle International Corporation

Mediatek Singapore Pte. Ltd.

Sushil Kumar

Karl Dias

Mark Charles Ramacher

Graham Wood

Leng Leng Tan

Benoit Dageville

Tirthankar Lahiri

Gary C Ngai

Chetan Deshpande

Alex Tsukerman

Gianfranco Putzolu

Gajanan Sahebrao Jedhe

Gaurang Prabhakar Narvekar

Richard Sarwal

Yunrui Li

Uri Shaft

Mohamed Ziauddin

Vasudha Krishnaswamy

Sujatha Muthulingam

Venkateshwaran Venkataramani

Cheng-Xin Xue

Wanli Yang

Ritesh Garg

Vishwanath Karra

Francisco Sanchez

Shivani Gupta

Michael Feng

Zijie Guo

Hsiao-te Su

Qiang Cao

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Memory array with programmable number of filters

A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Dynamically gated search lines for low-power multi-stage content addressable memory

One or more usage models are provided for a database. Each usage model includes a set of rules that are used to analyze database performance. A usage model in one or more usage models is determined. Database information is determined based on the usage model. The database information is then analyzed based on rules associated with the usage model. One or more performance problems are determined based on the analysis.

Automatic database diagnostic usage models

A self-managing workload repository (AWR) infrastructure useful for a database server to collect and manage selected sets of important system performance statistics. Based on a schedule, the AWR runs automatically to collect data about the operation of the database system, and stores the data that it captures into the database. The AWR is advantageously designed to be lightweight and to self manage its use of storage space so as to avoid ending up with a repository of performance data that is larger than the database that it is capturing data about. The AWR is configured to automatically capture snapshots of statistics data on a periodic basis as well as purge stale data on a periodic basis. Both the frequency of the statistics data capture and length of time for which data is kept is adjustable. Manual snapshots and purging may also be performed. The AWR captured data allows for both system level and user level analysis to be automatically performed without unduly impacting system performance, e.g., by eliminating or reducing the requirement to repeat the workload in order to diagnose problems.

Self-managing performance statistics repository for databases

An intelligent database infrastructure wherein the management of all database components is performed by and within the database itself by integrating management of various components with a central management control. Each individual database component, as well as the central management control, is self-managing. A central management control module integrates and interacts with the various database components. The database is configured to automatically tune to varying workloads and configurations, correct or alert about bad conditions, and advise on ways to improve overall system performance.

Self-managing database architecture

A method for simulating different MTTR settings includes determining a simulated MTTR setting and providing a simulated checkpoint queue. The simulated checkpoint queue is associated with the simulated MTTR setting and is an ordered list of one or more elements. Each element represents a buffer, and the ordered list has a head and a tail. The method also includes providing a simulated write counter associated with the simulated MTTR setting. The method further includes, in response to detecting a change to a first buffer, checking if the first buffer is represented in the simulated checkpoint queue. If the first buffer is not represented in the simulated checkpoint queue, an element that represents the first buffer is linked to the tail of the simulated checkpoint queue. An MTTR advisory system includes a memory, one or more processors coupled to the memory, a simulated MTTR setting, a simulated checkpoint queue, and a simulated write counter. The simulated MTTR setting is maintained in the memory. The simulated checkpoint queue is maintained in the memory and associated with the simulated MTTR setting. The simulated write counter is also maintained in the memory, and is associated with the simulated MTTR setting. The simulated write counter provides a count of the number of times an element is removed from the simulated checkpoint queue, wherein the element is removed from the simulated checkpoint queue in response to a write out of a buffer from volatile memory and storing in nonvolatile memory.

Mean time to recover (MTTR) advisory

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San Jose, CA, United States of America

Sushil Kumar