Texas Instruments Corporation

Sushil Kumar Gupta

Arup Dash

A master latch implemented to receive feedback from a slave latch on a different input terminal than a input terminal on which data bits are received. Due to such receiving, the number of transistors/area and/or power consumption requirements (efficiently) may be minimized in implementing a flip-flop. The feedback path may be implemented using a single pass-gate, further enhancing the efficiency of implementation. In addition, clock enable/disable signals may be generated efficiently taking into account an externally received flip-flop disable signal and absence of transitions in the data input bits. When the flip-flop is implemented to support ATPG type sequential scanning testing, a multiplexor may be implemented efficiently to select either the data bits or scan bits.

Reducing power and area consumption of gated clock enabled flip flops

A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback driver circuits minimize (prevent) an amount of time both the NMOS and PMOS transistors are in an ON state at the same time, thereby reducing short circuit power (i.e., the power dissipated if both the PMOS and NMOS transistors are in an on state). In addition, as the two feedback driver circuits do not contain common input inverter circuits, the short circuit power is further reduced.

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Lucknow, India

Sushil Kumar Gupta