Crosscheck Technology, Inc.

Susheel J Chandra

Tushar R Gheewala

During application of a sequence of design verification patterns at the primary input pins of a sequential circuit IC, a test vector is spliced between patterns to test for a fault condition. As design verification patterns are applied in sequence, the state of the sequential circuit changes. To test for a select fault condition, the sequential circuit needs to be in a desired state. While in such desired state, a test vector is applied and select internal circuit element responses are monitored. If the desired state occurs during a sequence of design verification patterns, then the test vector is applied between successive patterns before the IC clock has a transition. By applying the test signal, monitoring the response, then reapplying the design verification pattern before the clock changes, the IC subsequent state which would occur had the test vector been omitted still occurs. If a desired state does not occur during the sequence of design verification patterns, then a select state similar to the desired state is identified. When such select state occurs, control signals are applied through internal test points to force a state change to the desired state. Thereafter, the appropriate test vector is applied and the response is monitored to check the fault condition. All such steps occur before a clock transition so that the state and design verification pattern occurring at the beginning of the clock cycle, also occur before the next transition to the clock cycle. Accordingly, the design verification pattern sequence is not invalidated.

Method for testing a sequential circuit by splicing test vectors into

An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers. To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and to address other select test points at which response signals are to be sensed. Control signals are produced from the data register contents. The data register contents are derived as a function of the prior contents of the data register and a bit pattern formed from response signals of select test points. According to one embodiment, the prior contents are exclusively or'ed with the bit pattern of response signals to derive the new data register contents. A continuous test is performed by using prior response signals exclusively OR'ed to data register contents so as to generate subsequent control signals. Predesigned test sequences enable fast continuous testing of the IC.

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Fremont, CA, United States of America

Susheel J Chandra