Intel Corporation

Susheel G Jadhav

Mukul P Renavikar

Daoqiang Lu

Quan Anh Tran

Carl L Deppisch

Thomas John Fitzgerald

Raiyomand F Aspandiar

Ankur Agrawal

Kenneth Brown

Priyanka Dobriyal

Nitin A Deshpande

John Heck

Fay Hua

Ling Liao

Raghuram Narayan

David Hui

Syed S Islam

Kenneth M Brown

Embodiments described herein may be related to apparatuses, processes, and techniques related to packages that include CPUs and PICs electrically coupled via an interconnect bridge. In embodiments, the PIC are electrically coupled with the EMIB using a fan out RDL to extend reach of the PIC electrical connectors. EICs may be electrically coupled between the PIC and the interconnect bridge. The CPUs may be CPUS, graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other processors. Other embodiments may be described and/or claimed.

Integrated photonics and processor package with redistribution layer and EMIB connector

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.

Silicon photonic integrated lens compatible with wafer processing

An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.

Decoupling layer to reduce underfill stress in semiconductor devices

A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120&#xb0; C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.

Solder deposition and thermal processing of thin-die thermal interface material

Some embodiments of the invention include a coated thermal interface to bond a die with a heat spreader. The coated thermal interface may be used to bond the die with the heat spreader without flux. Other embodiments are described and claimed.

Coated thermal interface in integrated circuit die

An integrated heat spreader and die coupled with solder are disclosed herein. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.

Integrating a heat spreader with an interface material having reduced void size

Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps, comprises a solder. The method also includes forming a metal region including indium and tin, on at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps. The method also includes positioning the first metal bumps on the second metal bumps, and heating the metal bumps and the metal region and melting the solder. Other embodiments are described and claimed.

Methods including fluxless chip attach processes

Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.

Integrated heat spreader with intermetallic layer and method for making

Integrated heat spreader and die coupled with solder. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.

Integrated heat spreader and method for using

Disclosed are embodiments of a method of attaching a die to a substrate and a heat spreader to the die in a single heating operation. A number of conductive bumps extending from the die may also be reflowed during this heating operation. Other embodiments are described and claimed.

Method for attaching a semiconductor die to a substrate and heat spreader

An apparatus and system, as well as fabrication methods therefor, may include a die having a surface and a primary material comprising tin, pure tin, or substantially pure tin coupled to the surface. A heat dissipating element may be coupled to the primary material.

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Chandler, AZ, United States of America

Susheel G Jadhav