Samsung Electronics Co., Ltd.

Sushant Kondguli

Arun Radhakrishnan

Nilanjan Goswami

David Conrad Tannenbaum

Santosh Abraham

Wilson Wai Lun Fung

Zhenhong Liu

Wayne Yamamoto

Zachary Neyland

Anshujit Sharma

A graphics processing unit (GPU) includes a table located in a memory of the GPU and a cache hierarchy. The table contains an address of inactive data in a cache hierarchy of the GPU in which the inactive data is associated with an intermediate render target. The cache hierarchy is responsive to an eviction event by discarding the inactive data from the cache hierarchy without performing a writeback to a system memory associated with the GPU based on the address of the inactive data being contained in the table. The cache hierarchy may obtain the address of the inactive data from the table, and the inactive data may be located in a last-level cache of the cache hierarchy. In one embodiment, the address of inactive data in a cache hierarchy of the GPU includes a range of addresses for the inactive data.

Systems, methods, and devices for discarding inactive intermediate render targets

A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

Methods and apparatus for implementing cache policies in a graphics processing unit

A method to process tiles of a screen space includes determining a tile-processing order for tiles of a first batch of primitives based on a tile-processing order for a second batch of primitives in which the second batch of primitives are processed prior to the first batch of primitives. The tiles of the first batch of primitives are processed based on the tile-processing order determined for the tiles of the first batch of primitives. The tile-processing order is updated as tiles of the first batch of primitives are pushed to a backend processing portion of a graphics processing unit. In one embodiment, determining the tile-processing order for the tiles of the first batch of primitives include arranging the tiles of the first batch of primitives that have a same screen-space as tiles of the second batch of primitives based on a most-recently-processed-tile-to-a-least-recently-processed tile order of the second batch of primitives.

Re-reference aware tile walk order for primitive binner

A method includes determining that a new draw call is received; comparing a state identity (ID) of a graphics state stored in the ring storage with a state ID of a graphics state associated with the new draw call; determining if the ring storage has available space to store the graphics state associated with the new draw call; storing the graphics state associated with the new draw call in the ring storage, based on determining that the ring storage has available space; determining a location of a first valid and non-default entry and a last valid and non-default entry of the graphics state associated with the new draw call stored in the ring storage; and collecting data from one or more valid entries of the graphics state associated with the new draw call stored in the ring storage to complete a task associated with the new draw call.

Variable entry transitional ring storage for efficiently accessing graphics states

A system and a method are disclosed that reduce primitive overdraw in a GPU. An occlusion index (OI) for a first tile of a batch of graphical data. In one embodiment, the first tile is bypassed from an early coverage discard (ECD) first-in, first-out (FIFO) if the OI for the first tile is less than a first threshold, otherwise the first tile is entered into the ECD FIFO. The first tile is also bypassed from the ECD FIFO if the OI for the first tile is greater than a second threshold that is greater than the first threshold. In another embodiment, a queue length is logically changed for the first tile in the ECD FIFO if the OI for the first tile is greater than the first threshold and less than or equal to a third threshold that is greater than the first threshold and less than the second threshold.

Growing community of inventors

San Jose, CA, United States of America

Sushant Kondguli