Infineon Technologies Ag

Susanne Lachenmann

Valentin Rosskopf

Andreas Felber

Sibina Sukman-Praehofer

Sibina Sukman

Ramona Winter

Valentine Rosskopf

Sibina Sukman-Prähofer

The invention relates to a semiconductor wafer () having a plurality of first sawing regions (-) running parallel to one another in a first direction (X) and a plurality of second sawing regions (-) running parallel to one another in a second direction (Y), having useful regions () which in each case contain an integrated circuit () and which are in each case arranged between respective adjacent first sawing regions (-) and respective adjacent second sawing regions (-), and at least one test structure region arranged in the first sawing regions (-) and the second sawing regions (-) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts (-) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R) and a second row (R), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).

Semiconductor wafer with test structure

A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called 'buried straps', without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.

Semiconductor product having a semiconductor substrate and a test structure and method

A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.

Test structure for a single-sided buried strap DRAM memory cell array

A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.

Growing community of inventors

Munich, Germany

Susanne Lachenmann