Control Data Corporation

Susana Stoica

A method for designing integrated circuits for improved testability. A main logic function operable in initialization and test modes is defined in terms of component logic macros. Testability circuitry for generating CLEAR, CLEAR0 and CLEAR1 testability signals is also defined. The CLEAR signals have the first logic state during system operation in the initialization mode, and first and second logic states equal amounts of time during the test mode. The CLEAR0 signals have the first logic state during the initialization mode, and have the second logic state most of the time and the first logic state the remainder of the time during the test mode. The CLEAR1 signals have the first logic state during the initialization mode, and have the first logic state most of the time and the second logic state the remainder of the time during the test mode. First-type macros, such as multiplexers having Select or other inputs requiring CLEAR signals during the test mode, are identified. Second-type macros such as flip flops having clear, set or other inputs requiring CLEAR0 signals during the test mode are identified. Third-type macros such as flip flops having Enable or other inputs requiring CLEAR1 signals during the test mode are identified. Interconnections between the identified first, second and third-type macros and associated CLEAR, CLEAR0 and CLEAR1 signals are defined. Both logic and timing simulations and testability analysis on the integrated circuit can then be performed before the main logic function is redefined.

Logic circuit and design method for improved testability

A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. It is adaptable to custom or semi-custom VLSI chip design and it teaches that any 'component' (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data). The test data output can be transmitted in parallel between the flip flop ranks, or it can go serially through the flip flop components of a given rank.

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Edina, MN, United States of America

Susana Stoica