Intel Corporation

Tandem Computers Incorporated

Susan S Meredith

D Michael Bell

Mark A Gonzales

David J Garcia

William P Bunton

John D Coddington

William J Watson

David P Sonnier

Eric Dahlen

John C Krause

William Edward Baker

Geoffrey I Iswandhi

Daniel L Fowler

Frank A Williams

Linda Ellen Zalzala

Paul N Hintikka

Robert W Horst

David M Lee

John Michael Brown

Dave B Minturn

William F Bruckert

Douglas E Jewett

Richard W Cutts, Jr

Steven C Meyers

Stephen G Low

David L Chalupsky

Patricia L Whiteside

Randall G Banton

James Stevens Klecka

Kenneth C Holland

Warren R Morrow

Gary F Campbell

John L Baudrexl

Curtis Willard Jones, Jr

Stephen H Miller

Wendell S Wenjen

Barry Lee Drexler

Harry Frank Elrod

An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command. There may be arranged a completion monitoring unit arranged to monitor for completion of the converted second predetermined command by the external recipient as an indication that an operation with respect to the first predetermined command has been completed. The second predetermined command may be a read-type command, where the completion monitoring unit is arranged to monitor for return of data from the external recipient responsive to the read-type command, as an indication that an operation with respect to the first predetermined command has been completed. The first predetermined command may be a FLUSH command for forcing existing commands to be sent to external recipients for completion. The command translation/ordering unit may be part of a first integrated circuit (IC), where the command translation/ordering unit converts the first predetermined command into a second predetermined command recognizable/supported by a second IC as the external recipient.

Method and apparatus for command translation and enforcement of ordering of commands

A bus bridging method, a bus bridge and a bus agent are described. In a bus agent provides to a bus bridge a read data request targeting a data source bridged by the bus bridge. The read data request includes a read address indicating a starting storage location of the requested data, and a read size indicator indicating the size of the requested data. The bus bridge, in response, facilitates provision of the requested data to the bus agent. The facilitation includes streaming buffered ones of the requested data to the bus agent through one or more successive streaming connections to the bus bridge by the bus agent.

Bus bridging method and apparatus including use of read size indicators

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Detecting and isolating errors occurring in data communication in a

A computer system includes a bus, a first bus device, a core circuit and a second circuit. The first bus device is coupled to the bus and adapted to finish a first indication of data to a portion of a bus beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus beginning at another clock cycle. The second circuit is coupled to the bus and is adapted to receive an indication of a selected latency time. The second circuit is also adapted to transfer the data to the core circuit in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.

Regulating a data transfer time

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus. The TAU determines whether posting to the inbound request queue is enabled or disabled; whether any posted transactions exist in the inbound request queue; and whether ownership of the second bus is available.

Method and apparatus for maintaining transaction ordering and

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.

Interrupt message delivery identified by storage location of received

An apparatus for configuring multiple agents in a computer system includes a first storage device for storing a set of configuration values and a second storage device for capturing the set of configuration values from the bus. These configuration values are driven onto the bus and retrieved from the bus by interface logic within the apparatus. The interface logic drives the configuration values onto the bus when a register within the apparatus is activated. At system power-on, the first storage device defaults to a first set of values. These values are then driven onto the bus and retrieved by each agent on the bus, including the apparatus of the present invention. This first set of values provides the system with the necessary parameters to access and execute certain initialization program(s). These initialization programs can modify the configuration values stored in the first storage device. After the initialization program(s) modify the first storage device, they activate a register within the apparatus of the present invention. This register causes interface logic to drive the values stored in the first storage device onto the system bus. Each agent on the bus, including the apparatus of the present invention, retrieves these values. The apparatus of the present invention stores these values in a second storage device and proceeds to operate according to the values in the second storage device.

Method and apparatus for configuring multiple agents in a computer system

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue. Both the outbound request queue and the inbound request queue have data buffers associated therewith for transferring data between the two buses. In addition, requests may originate on the second bus which target a device on the first bus (i.e., inbound requests). These inbound requests are placed in the inbound request queue and are executed on the first bus when removed from the inbound request queue.

Method and apparatus for maintaining transaction ordering and supporting

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Hillsboro, OR, United States of America

Susan S Meredith