National Semiconductor Corporation

Fairchild Semiconductor Corporation

Susan M Keown

Roy L Yarbrough

Geoff Hannington

Dana J Fraser

Ray A Mentzer

Gaetan L Mathieu

Jerry Gray

Myron J Miske

A BICMOS input buffer circuit (20) incorporates an integral CMOS passgate circuit (P2,N2) between bipolar input (Q1) and output (Q3,Q4,Q5) transistors of the input buffer circuit. Latch enable inputs (LE) receive latch enable signals for operating the input buffer circuit and internal passgate in a transparent mode for passing data signals from the input (V.sub.IN) to the output (V.sub.OUT) and in a blocking mode for blocking data signals. The internal CMOS passgate circuit (P2,N2) is coupled into the input buffer circuit (20) to control nodes of the transistor output pullup (Q4,Q5) and pulldown (Q3) for controlling the conducting states of the respective transistor output pullup and pulldown to implement the blocking and transparent modes. A third passgate transistor (P3) may also be coupled between a control node (m1) of the transistor output pullup (Q4,Q5) and the low potential power rail (GND) for positive turn off of the output pullup. A dynamic power enhancement circuit (DPC) provides transient enhancement for the transition from the blocking mode to transparent mode.

BICMOS input buffer circuit with integral passgate

A wafer structure and a method of fabricating and testing IC dies (10) on a wafer (12) are incorporated in a wafer fabrication process which produces IC dies having a selected sensitive AC parameter (L.sub.EFF,.beta.,R). Performance of the sensitive AC parameter generally falls within a first range of variation characteristic of the wafer fabrication process. A test structure or test pattern (TNMOS, TPMOS, TNPN, TR) is formed on substantially every die (10) of the wafer (12) for testing in a DC parametric test at the wafer level sorting stage before scribing and packaging the dies from the wafer. The test structures are constructed for generating test measurements in a DC parameter test reflecting the AC performance of the selected sensitive AC parameter. Substantially every die on the wafer is tested at the wafer level sorting stage using the test structures (TNMOS, TPMOS, TNPN, TR) in a DC parametric test. Those dies of the wafer reflecting AC performance of the selected sensitive AC parameter (L.sub.EFF, .beta., R) within a second range of variation narrower than the first range are selected for packaging. The other dies of the wafer are rejected or sorted for other purposes before packaging for increasing the yield of packaged IC dies meeting AC specifications for AC performance within the narrower second range. The test structures include test NMOS (TNMOS) and test PMOS (TPMOS) transistors for test indication of effective gate length L.sub.EFF for CMOS transistors; test NPN transistors (TNPN) for reflecting the amplification factor .beta. for bipolar NPN transistors; and test resistors (TR) for test indication of effective resistance, isolation oxide encroachment, overetch or underetch, etc.

Individualized prepackage AC performance testing of IC dies on a wafer

In a BiCMOS TTL output buffer circuit, bipolar output pullup and pulldown transistors (Q3,Q4,Q5) source and sink current at an output (V.sub.OUT). A phase splitter transistor (Q2,N4) is coupled to the bipolar output pullup and pulldown transistors for controlling respective conducting states in response to data signals at an input (V.sub.IN) during the active bistate mode of operation. CMOS tristate transistors (P1, ,P2,P4,N2) form a tristate circuit for implementing an inactive tristate mode at the output V.sub.OUT in response to tristate enable signals at a tristate enable input (OE). In order to reduce quiescent input current (I.sub.CC) power dissipation, an input power switch CMOS transistor (NI,N4,P1A) is coupled in the input current path to the high potential power rail (V.sub.CCI). The control gate node of the input power switch CMOS transistor (N1, ,N4,P1A) is coupled to the input (V.sub.IN) to control sourcing of input current (I.sub.CC) in response to data signals at the input during the active mode for reducing power dissipation. In the preferred example the input power switch CMOS transistor (N4) replaces and comprises the phase splitter transistor of the output buffer circuit. Dual CMOS phase splitter transistors (N4,N3) are also provided with the second dual CMOS phase splitter transistor (N3) coupled in an accelerating feedback circuit between the output (V.sub.OUT and the output pulldown transistor (Q5).

BiCMOS TTL output buffer circuit with reduced power dissipation

Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.

Transceiver with isolated power rails for ground bounce reduction

A V.sub.OH clamp circuit reduces propagation delay time TP.sub.HL and reduces ground bounce noise in TTL output buffer circuits. First and second band gap bias generators (BG1,BG2) coupled in series provide a substantially stable clamp reference voltage level (V.sub.R) over a specified range of operating temperatures. The clamp reference voltage level (V.sub.R) is referenced to the low potential power rail (GND). Voltage drop components (D32,QC) of the Y.sub.OH clamp circuit couple the reference voltage level (V.sub.R) through the voltage drop components (D32,QC) to an internal node, namely the base node (BDAR) of the pullup Darlington configuration transistor pair (Q12A,Q12B), The V.sub.OH clamp circuit clamps the high potential level output signal (V.sub.OH) at a maximum voltage level (V.sub.OHMAX) less than the high potential level power rail (V.sub.cc), and referenced to the clamp reference voltage level (V.sub.R). The band gap bias generator circuit (BG1,BG2) establishes a substantially stable clamp reference voltage level (V.sub.R) approximately equal to the output signal maximum voltage level (V.sub.OHMAX). The V.sub.OH clamp circuit voltage drop components (D32,QC) establish a step up voltage drop approximately equal to the step down voltage drop across the pullup Darlington transistor pair (Q12A,Q12B).

TTL output buffer with temperature compensated V.sub.oh clamp circuit

To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe. An additional lead is obtained from a conductive element originating near the paddle and supported by one of the two lead frame rails.

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Portland, ME, United States of America

Susan M Keown