Hrl Laboratories, LLC

The Boeing Company

Susan L Morton

Donald A Hitko

Albert E Cosand

Mark J Rodwell

Ken Elliott

Chan-Tang Tsen

Peter Petre

Carson R White

Jose Cruz-Albrecht

Joseph S Colburn

Zhiwei A Xu

Yen-Cheng Kuan

Michael W Yung

David S Matthews

Alan E Reamon

Jason W May

Ining Ku

A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

Multiplexing sample-and-hold circuit

A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.

Dual edge pulse de-multiplexer with equalized path delay

A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as 'non-Foster circuits.' The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Differential negative impedance converters and inverters with variable or tunable conversion ratios

Disclosed is a time delay generatorapparatus and method. The apparatus includes a time delay gate, a mixer(a Gilbert cell circuit), and a current digital to analog converter. The mixer, comprised of first and second transistor differential pairsand, receives an analog input signalwithout a delay as well as a delayed input signalproduced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signaland a second control signal, effectively altering the mixing of the undelayed input signaland the delayed input signalto generate a delayed output signalwith a time or phase delay substantially equal to the temporal delay represented by the digital signal input. The time delay generator exhibits reduced phase noise and a linear time delay response.

Time delay apparatus and method of using same

A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.

High speed divider circuit

A linearized folding amplifier circuit ( ) includes a comparator ( ) that has a first state and a second state, and a switched output circuit that has a pair of outputs. The non-linearity in the response of a differential transistor pair to an input signal is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween that is replicated from the differential error in the base-voltages emitter voltages of the input differential pair. The output of the circuit is the combination of the partially linearized portion from the first resistor and a linearized transconductor circuit that has an output formed in response to the differential error.

Linearized folding amplifier

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Pittsford, NY, United States of America

Susan L Morton