Motorola Corporation

Susan L Gilfeather

John B Gehman, Jr

Calvin W Harrison

Bruce Alan Fette

James Edward Greenwood, Jr

A memory linked address generator and method for a complex arithmetic processor executing an algorithm sequence includes memories, a clock for generating a clock cycle, and a decoder for determining position of the complex arithmetic processor within the algorithm sequence. The decoder is coupled to the clock and address pointer generators are coupled to the decoder and to the memories. The address pointer generators generate address pointers within the clock cycle for at least some of the memories in response to the position of the complex arithmetic processor within the algorithm sequence.

Parallel process address generator and method

An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.

Arithmetic engine with dual multiplier accumulator devices

A complex arithmetic processor and method includes a host interface for distributing data, a left memory and a right memory each coupled to the host interface, and a Z memory coupled to the host interface. The left memory and the right memory store the data and the Z memory stores Z memory data. A right/left switch is coupled to the left memory and to the right memory and makes left memory a data source and a right memory a data destination in a first setting, and makes the right memory the data source and the left memory the data destination in a second setting. An arithmetic engine is coupled to the host interface, to the Z memory, and to the left and right memories. The arithmetic engine uses the data and the Z memory data to perform an operation on the data to produce a result.

Complex arithmetic processor and method

A special functions arithmetic logic unit (ALU) method and apparatus includes an ALU register, an ALU register value processor coupled to the ALU register for receiving and processing ALU register values to produce output data, and a normalizer. The normalizer receives and processes complex memory values to produce normalized output data independently of the output data from the ALU register value processor. The ALU register value processor includes a parser, combiner, polynomial divider, magnitude estimator, and a Hamming distance determiner. The normalizer includes an exponent determiner and first and second scalers for producing normalized X and Y data of the normalized output data.

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Scottsdale, AZ, United States of America

Susan L Gilfeather