International Business Machines Corporation

Globalfoundries Inc.

Susan K Lichtensteiger

Jeanne P Bickford

Eric A Foreman

Mark William Kuemerle

Sebastian Theodore Ventrone

Nazmul Habib

Theodoros Anemikos

Igor Arsovski

Jeanne H Raymond

David James Hathaway

Michael Richard Ouellette

Chandramouli Visweswariah

Peter Anton Habitz

John Maxwell Cohn

Jeffrey G Hemmett

Nathan C Buck

Pascal A Nsame

Anthony D Polson

Robert J McMahon

Thomas Gregory Sopchak

Troy Joseph Perry

Paul J Grzymkowski

Laura S Chadwick

Raymond W M Schuppe

David M Picozzi

Natesan Venkateswaran

Douglas Willard Stout

David E Lackey

Daniel Lawrence Stasiak

Howard Hao Chen

Alvar Antonio Dean

Tad Jeffrey Wilder

John P Dubuque

Patrick H Buffet

Ivan L Wemple

Larry Wissel

Richard Andre Wachnik

Brian M Dreibelbis

Kevin K Dezfulian

Jeanne P S Bickford

James Charles Gregerson

Xiaoyue X Wang

Scott Alan Tetreault

James Patrick Eckhardt

Raymond J Rosner

Timothy M Platt

Thomas M Lepsic

Bruce Balch

Jeanne Paulette Spence Bickford

Thomas S Barnett

James J Engel

William F Smith

Phillip Paul Normand

Kevin Grosselfinger

Jeanne P Spence Bickford

John S Gregor

Paul J Sulva

Rebecca A Bickford

Clarence C Hubbell

William Smith

A method and associated system. The method includes steps of: (a) a voltage bin is selected from of a set of voltage bins, each voltage bin having a different range of frequencies based on the highest operating frequency and the lowest operating frequency specified for an integrated circuit chip not previously tested; (b) a functional path test is performed on a selected path of a set of testable data paths of the integrated circuit chip not previously tested; (c) if the integrated circuit chip fails the functional path test, then a current supply voltage value is changed to a voltage value associated with a not previously selected voltage bin; (d) a not previously tested path of the set of testable paths is selected. Steps (b), (c) and (d) are repeated until every path of the set of testable paths has been tested.

Product performance test binning

Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Pre-test power-optimized bin reassignment following selective voltage binning

A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.

Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified.

Timing/power risk optimized selective voltage binning using non-linear voltage slope

Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Selective voltage binning leakage screen

Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

Integrated circuit chip design methods and systems using process window-aware timing analysis

Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling

Disclosed is a system that periodically increases the supply voltage applied to a power rail of an integrated circuit chip that is incorporated into a product, thereby compensating for age-dependent changes in a performance parameter sensitivity (e.g., in a delay sensitivity). In this system, the chip comprises at least a memory, an age monitor, a voltage selector and a power rail. The memory stores an age/voltage table. The age monitor automatically measures the age of the chip. Based on the age and using the age/voltage table, the voltage selector selects a specific supply voltage and outputs a voltage selection signal to an adjustable voltage regulator, which can apply (e.g., automatically or on-demand) that specific supply voltage to the power rail. Also disclosed is a method for regulating the power supplied to an integrated circuit chip, which is incorporated into a product, and a method for generating an age/voltage table.

System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time

Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.

Systems and methods for system power estimation

Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Controlling circuit voltage and frequency based upon location-dependent temperature

A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.

Power/performance optimization through continuously variable temperature-based voltage control

A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.

Power/performance optimization through temperature/voltage control

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Essex Junction, VT, United States of America

Susan K Lichtensteiger