International Rectifier Corporation

Infineon Technologies Americas Corp.

Susan Johns

David Paul Jones

Robert J Montgomery

Hugo R Burke

Philip Parsonage

Mark Pavier

Andrew Neil Sawle

Daniel Cutler

Martin Carroll

Danish Khatri

Phillip Parsonage

A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Power semiconductor device with a double metal contact and related method

Power semiconductor device with a double metal contact

Power semiconductor device including a double metal contact

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Autoclave capable chip-scale package

The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected. The result is an antifuse that is well isolated from other wiring and a standard via that will facilitate good electrical contact between metal layer and

Design and processing of antifuse structure

Growing community of inventors

Cardiff, United Kingdom

Susan Johns