International Business Machines Corporation

Susan J LaMaire

David Andrew Lewis

George Frederick Walker

Alfred Viehbeck

Kwong Hon Wong

Sudipta Kumar Ray

Daniel George Berger

Umar M Ahmad

Keshav B Prasad

Joseph J Van Horn

Jer-Ming Yang

Yuk L Tsang

Jeffrey A Haley

Kathleen S Ginn

Ananda Kumar

Peter E Freiermuth

Clarence S Long

Timothy A Redmond

Gavin T Mills

The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.

Method and apparatus for stressing, burning in and reducing leakage

A control element positioned between an object being heated and a source of microwave radiation is employed to prevent a localized concentration of microwave energy resulting from a discontinuity in the object surface. Close control is provided for heating an object with a sensitive coating.

Uniform microwave heating

In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

Selective plating method for forming integral via and wiring layers

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Yorktown Heights, NY, United States of America

Susan J LaMaire