Microsoft Technology Licensing, LLC

Sun Microsystems, Inc.

Extreme Networks, Inc.

Silicon Graphics, Incorporated

Susan Elizabeth Carrie

Jerald R Evans

Jeffrey Andrews

Sheue-Ling Lien

Erik De La Iglesia

Rahoul Puri

George Easton Scott, Iii

James Van Loo

Serdar Ergene

Michael J Shantz

Ravi Shankar Kolli

Wei W Wang

Christopher Douglas Edmonds

Adam James Muff

Ratinder Paul Singh Ahuja

John Allen Tardif

John Grant Bennett

James A Gosling

Mark James Finocchio

Nhon Toai Quach

Alessandro Forin

John Victor Sell

Kyungsuk David Lee

Ankur Varma

Kiet Tuan Tran

Hui Zhang

Miguel Gomez

Jason K Oberg

Padma Parthasarathy

Ricky K Lowe

Rune Hartung Jensen

Mark Aaron Wallace

Liang Liu

Victor Tirva

Chien C Chou

Todd E Wayne

David H Elrod

Randy Crane

Ken Eguro

Vijay Balakrishnan

David Elrod

Jim V Loo

Jeffrey Spirn

Derek Bosch

Jonathan Chow

Ravi Shankar Reddy Kolli

Kevin Po

Jim Van Loo

John Sell

The generation of symbol-encoded data from digital data, as part of the compression of the digital data into a compressed digital data, can be performed with reference to multiple alternative alphabets. A selection of a specific alphabet is made based on the digital data being compressed, the compression parameters, or combinations thereof. Information indicative of the selected alphabet is encoded into one or more headers of the resulting compressed digital data. A single alphabet can be selected for all of a set of digital data being compressed, or multiple different alphabets can be selected, with different ones of the multiple different alphabets being utilized to compress different portions of the digital data. Additionally, rather than explicitly specifying a specific selected alphabet, the header information can comprise information from which a same alphabet can be independently selected heuristically by both the compressor and the corresponding decompressor.

Computer data compression utilizing multiple symbol alphabets and dynamic binding of symbol alphabets

A data compression system includes a memory to store a plurality of predetermined prefixes corresponding to a plurality of classes of data. A classifying module is configured to receive data, receive a class of the data, and select a prefix to compress the data from the plurality of predetermined prefixes based on the data and the class of the data. A compressing module is configured to compress the data using the prefix. A header generating module is configured to generate a header including an indication of the prefix used to compress the data, and to output the header and the compressed data for storage or transmission. Using the prefix from the predetermined prefixes to compress the data eliminates an overhead of fetching the prefix from outside the data compression system.

Use of data prefixes to increase compression ratios

A method for refining multithread software executed on a processor chip of a computer system. The envisaged processor chip has at least one processor core and a memory cache coupled to the processor core and configured to cache at least some data read from memory. The method includes, in logic distinct from the processor core and coupled to the memory cache, observing a sequence of operations of the memory cache and encoding a sequenced data stream that traces the sequence of operations observed.

Processor cache tracing

Methods and systems for selectively processing VLAN traffic from different networks while allowing flexible VLAN identifier assignment are disclosed. According to one aspect, a layer 2 switch includes a virtual switch identifier data structure that associates a VLAN identifier extracted from a layer 2 frame and a port identifier corresponding to a port on which a frame is received with a virtual switch identifier. The virtual switch identifier is used to select a per-virtual-switch data structure, such as a forwarding table. The per-virtual-switch data structure is used to control processing of the layer 2 frame on a per-virtual-switch basis. The per-virtual-switch data structure may also be updated separately from the data structures assigned to other virtual switches.

Methods and systems for selectively processing virtual local area network (VLAN) traffic from different networks while allowing flexible VLAN identifier assignment

Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.

Fine-grained bandwidth provisioning in a memory controller

Embodiments are disclosed that relate to processing image pixels. For example, one disclosed embodiment provides a system for classifying pixels comprising retrieval logic; a pixel storage allocation including a plurality of pixel slots, each pixel slot being associated individually with a pixel, where the retrieval logic is configured to cause the pixels to be allocated into the pixel slots in an input sequence; pipelined processing logic configured to output, for each of the pixels, classification information associated with the pixel; and scheduling logic configured to control dispatches from the pixel slots to the pipelined processing logic, where the scheduling logic and pipelined processing logic are configured to act in concert to generate the classification information for the pixels in an output sequence that differs from and is independent of the input sequence.

System and method for classifying pixels

A computing device for use in decision tree computation is provided. The computing device may include a software program executed by a processor using portions of memory of the computing device, the software program being configured to receive user input from a user input device associated with the computing device, and in response, to perform a decision tree task. The computing device may further include a decision tree computation device implemented in hardware as a logic circuit distinct from the processor, and which is linked to the processor by a communications interface. The decision tree computation device may be configured to receive an instruction to perform a decision tree computation associated with the decision tree task from the software program, process the instruction, and return a result to the software program via the communication interface.

Decision tree computation in hardware utilizing a physically distinct integrated circuit with on-chip memory and a reordering of data to be grouped

Software rendering and fine grained parallelism are utilized to reduce/avoid memory latency in a multi-processor (MP) system. According to one embodiment, the management of the transfer of data from one processor to another in the MP environment is moved into a low overhead hardware system. The low overhead hardware system may be a FIFO ('First In First Out') hardware control. Each FIFO may be real or virtual.

Reduction of memory latencies using fine grained parallelism and FIFO data structures

Power is dynamically conserved in a device by analyzing past processing performance of the device and predicting the amount of power required for future execution. In an example embodiment, a video frame is analyzed to determine what portion of the video frame was needed to render data. If less than the full video frame was needed, at least one power conservation technique is applied to the device for subsequent rendering of data. Power conservation techniques include adjusting the operating frequency of circuitry utilized to render data, adjusting the voltage applied to circuitry utilized to render data, and/or turning off/on circuitry utilized to render data.

Media device power conservation

A connection pacer and method for performing connection pacing in a network of servers and clients using a first-in-first-out ('FIFO') buffer.

Connection pacer and method for performing connection pacing in a network of servers and clients using FIFO buffers

A debugging architecture includes a set of debug counters for counting one or more events based on a set of signals from a device being monitored. The architecture provides for observing the outputs of the debug counters during operation of the device. The outputs of the counters are provided to an output bus (e.g., a Debug Bus) via an output bus interface during operation of the device being monitored. A data gathering system can access the output bus in order to gather the data from the counters for analysis.

Observing debug counter values during system operation

A hardware implemented transactional memory system includes a mechanism to allow multiple processors to access the same memory system. A set of timestamps are stored that each correspond to a region of memory. A time stamp is updated when any memory in its associated region is updated. For each memory transaction, the time at which the transaction begins is recorded. Write operations that are part of a transaction are performed by writing the data to temporary memory. When a transaction is to be recorded, the hardware automatically commits the transaction by determining whether the timestamps associated with data read for the transaction are all prior to the start time for the transaction. In this manner, the software need not check the data for all other processes or otherwise manage collision of data with respect to different processes. The software need only identify which reads and writes are part of a transaction.

Timestamp based transactional memory

Growing community of inventors

Mountain View, CA, United States of America

Susan Elizabeth Carrie