Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Susan Clay Vitkavage

Kurt George Steiner

Sailesh Mansinh Merchant

Edward Belden Harris

Pradip Kumar Roy

William Graham Easter

Sudhanshu Misra

Daniel Joseph Vitkavage

Scott Jessen

Huili Shao

Yaw S Obeng

Gerald Warren Gibson, Jr

Allen Yen

Steven Alan Lytle

Gerald W Gibson, Jr

Juli H Eisenberg

Steve Lytle

An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

Inductor formed in an integrated circuit

A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N&#x2014;H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N&#x2014;H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide. The hardmask and etch-stop layer enable the formation of a dual-damascene opening in the film stack, and the film structure of the present invention precludes N&#x2014;H base groups from diffusing from the low-k dielectric films and neutralizing acid catalysts in the photoresist used to define the dual damascene opening.

Split barrier layer including nitrogen-containing portion and oxygen-containing portion

A film structure includes low-k dielectric films and N&mdash;H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N&mdash;H base film is a TEOS oxide film which suppresses the diffusion of amines or other N&mdash;H bases from the N&mdash;H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

Structure and method for isolating porous low-k dielectric films

Integration of low dielectric material in semiconductor circuit structures

A method of surface treating a surface and semiconductor article is disclosed. A deposited surface layer on a substrate, such as a semiconductor surface, is treated and annealed within an alkyl environment of a chemical vapor deposition chamber to passivate the surface layer by bonding with the silicon and attaching alkyl terminating chemical species on the surface of the surface layer to aid in dehydroxylating the surface. The surface layer comprises a silicon-oxy-carbide surface layer having a carbon content ranging from about 5% to about 20% at the molecular level and a dielectric constant of about 2.5 to about 3.0.

Surface treatment anneal of hydrogenated silicon-oxy-carbide dielectric layer

A porous insulator material and method of manufacturing. The material comprises oxygen, silicon and hydrogen characterized by a density less than 2 g/cc. Alternately, the porous insulator material is characterized by a refractive index less than 1.45 for light at a wavelength between 633 nm and 673 nm, or by a Young's modulus less than 45 GPa. A method for manufacturing a semiconductor device includes providing a semiconductor layer with an upper surface for device formation and forming multiple levels of interconnect over the semiconductor layer, each level including a plurality of members. The members are electrically isolated from other members by decomposition of TEOS to form a porous layer between at least some of the members.

Low k dielectric insulator and method of forming semiconductor circuit structures

The present invention provides a method of manufacturing an interconnect structure within a substrate. The method includes forming an opening in a substrate, which may be a dielectric layer having a low k; for example, one where the dielectric constant ranges from about 3.9 to about 1.9. This method further includes forming a passivation layer within the opening and a photoresist within the opening and over the passivation layer. The passivation layer substantially or completely inhibits the diffusion of elements from the substrate that can deactivate a photo acid generator (PAG) within the photoresist, which prevents the photoresist from developing properly.

Method of manufacturing an interconnect structure having a passivation layer for preventing subsequent processing reactions

An apparatus for determining the endpoint in a chemical mechanical polishing operation used for polishing a metal-containing material includes an electrochemical cell and an electronic circuit. An acidic polishing slurry is used to oxidize the metal and the oxidized metal is included in an effluent slurry stream, a sample of which is provided to the apparatus. The apparatus includes a liquid-phase working electrode, a reference electrode and a solid electrolyte which allows for the interchange of ions between the electrodes. An electronic circuit is coupled to the electrode for monitoring the component activity of the effluent slurry stream by measuring the electric potential across the electrodes. When the measured electric potential changes, indicating a change in the composition of the effluent slurry, endpoint is indicated.

Chemical mechanical polishing endpoint apparatus using component activity in effluent slurry

A method for determining the endpoint in a chemical mechanical polishing operation used for polishing a metal-containing material. An acidic polishing slurry is used to oxidize the metal and the oxidized metal is included in an effluent slurry stream. The effluent slurry stream is directed into a vessel which forms an electrochemical cell. The component activity of the effluent slurry stream is monitored within the electrochemical cell by measuring the electric potential across the electrodes of the electrochemical cell. When the measured electric potential changes, indicating a change in the composition of the effluent slurry, endpoint is indicated.

Chemical mechanical polishing endpoint detection by monitoring component activity in effluent slurry

A method of semiconductor circuit fabrication utilizing the poly buffered LOCOS process is disclosed. Amorphous silicon is desirably formed by the decomposition of disilane at temperatures between 400-525.degree. C. The amorphous silicon exhibits less pits than what is produced by conventional processes. The absence of pits contributes to eventual substrate integrity.

Integrated circuit fabrication process

An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Integrated circuit having amorphous silicide layer in contacts and vias

A process for removing both the silicon nitride layer and polysilicon layer in a poly-buffered LOCOS process which utilizes hot phosphoric acid and nitric acid is disclosed.

Growing community of inventors

Orlando, FL, United States of America

Susan Clay Vitkavage