Texas Instruments Corporation

Susan A Curtis

Harish Venkataraman

Karan Singh Jain

Timothy Bryan Merkin

Vadim Valerievich Ivanov

David John Baldwin

Gary Franklin Chard

Gene B Hinterscher

Justin Patrick Vogt

Daniel A King

Scott Adam Morrison

Theodor W Mahler

A switch includes a power transistor configured to switch an input voltage to a load. The switch further includes a charge pump and a duty cycle controller. The charge pump is coupled to the power transistor and includes an enable input to cause the charge pump to be turned on and off. The duty cycle controller is coupled to the charge pump and is configured to duty cycle the charge pump based on a comparison of a signal of a gate of the power transistor to a reference signal.

Duty cycle-controlled load switch

A circuit and method for providing a current limiting feature in a low dropout ('LDO') linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.

LDO current limit control with sense and control transistors

A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, R, and feedback capacitor, C, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, Rand Rand wherein the other side of the feedback capacitor is coupled between Rand the output of the first amplifier, Ris connected to Vfrom one side and Rand Rfrom the other, Ris connected to Rand Rfrom one side and Cand output of the first amplifier from the other side, another resistor, Ris connect to the output of the first amplifier, Cand Rfrom one side and Ryet another resistor, and input of ampfrom the other, a second amplifier, Ampis connected to the Rand Rat one input and 1.5v at the other input, and wherein the output of the second amplifier is connected to Rand Rconnects to one input of the second amplifier and the output of the second amplifier.

Method, apparatus and system for level shifting of common mode voltage from input to output for capacitive feedback transimpedance amplifier

An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.

Integrated receiver and ADC for capacitive touch sensing apparatus and methods

Circuitry (-) for limiting the maximum amount of current (I) flowing through a first electrode (DRAIN) of a first transistor (T) includes an amplifier () having an output coupled by a conductor () to a control electrode of the first transistor and limiting circuitry () including reference current sensing circuitry (,T) having a reference current source (I). A reference current sensing transistor (T) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal () of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Current limiting circuitry and method for pass elements and output stages

An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Synchronous state machine with an aperiodic clock

A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

Fast-settling precision voltage follower circuit and method

A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current 'I' specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

Bus-hold circuit

An input circuit is provided which receives TTL voltage signals as input and transmits CMOS voltage signal levels. A separation transistor connected to a voltage divider network is included within the circuit to separate the two gates of a CMOS inverter from the TTL input such that one gate of the inverter is fully off when the other gate is on and fully on when the other gate is off. Thus internal ground voltage fluctuations during operation of the circuit are avoided.

TTL compatible BICMOS input circuit

The disclosure relates to a circuit for compensation for ground glitches in an integrated circuit wherein there is provided a glitch fix circuit wherein a node is responsive to a negative shift in the level of ground relative to Vcc to turn on a transistor and drain current to ground from the input circuits to transistors in the circuit under control. A feedback circuit is provided which is out of phase with the circuit input of the circuit being controlled and which is one Von above ground. This feedback circuit inhibits the glitch fix circuit in the event that the increase in voltage difference between the input to the circuit being protected and ground is a result of a high input signal rather than noise which lowers the ground level.

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Sherman, TX, United States of America

Susan A Curtis