Intel Corporation

Suryaprasad Kareenahalli

Zohar Bogin

Daniel Nemiroff

Balaji Vembu

Raul N Gutierrez

Chee Hak Teh

Amber D Huffman

Chai Huat Gan

Eli Elik Kupermann

David E Freker

Rajasekaran Andiappan

Amit S Bodas

Sridhar Ramaswamy

Robert J Royer, Jr

Rajeev K Nalawadi

Anoop Mukker

Kar Leong Wong

Yuli Barcohen

Joon Teik Hor

Elena Agranovsky

Mihir D Shah

Robert J Rover, Jr

Christopher D Kral

Christian Soby

Amit Kimelman

Raul Gutierrez

In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.

Method and apparatus to manage power usage in a processor

Described is an apparatus comprising: a processor operable to execute a virtual machine manager (VMM) which is to manage a virtual machine (VM) for a hardware intellectual property (IP) block; a communication fabric; and a hardware IP block coupled to the processor via the communication fabric, wherein the hardware IP block is to be coupled to a first set of one or more sensors, and wherein the VM and the hardware IP block are operable to process data collected from the first set.

Low power sensing apparatus and method using a combination of virtual machine and dedicated hardware intellectual property IP block

An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.

Methods and apparatuses for securing playback content

A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Repurposing NAND ready/busy pin as completion interrupt

In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.

Handling media streams in a programmable bit processor

In some embodiments an embedded processor is to participate in cryptographic key exchange with an audio software application, and a key exchange communication path is coupled between the audio software application and the embedded processor. Other embodiments are described and claimed.

Audio content protection

Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location.

Boundary detection in media streams

The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

Direct memory access engine physical memory descriptors for multi-media demultiplexing operations

Apparatuses, methods, and systems for paging instructions for a virtualization engine to local storage. An apparatus includes a processor, a physical device controller, a virtualization engine, system memory, and local storage. The physical device controller is to be shared by a plurality of virtual machines created by a virtual machine monitor installed on a processor. The virtualization engine is to represent the physical device controller as a plurality of virtual device controllers available to be allocated to the plurality of virtual machines. The local storage is separate from the physical memory to store instructions transferred from the system memory for execution by the virtualization engine.

Paging instruction for a virtualization engine to local storage

Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.

Method, apparatus and system for reduced channel starvation in a DMA engine

An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

Dynamic adaptive read return of DRAM data

The invention describes a technology for closing DRAM pages, wherein the invention allows for dynamically changing code streams by tracking the previous decisions made on page closes and adjusts dynamically during DRAM operation to compensate for bad page close decisions made.

Dynamic update adaptive idle timer

Embodiments of a memory scoreboard are presented herein. The memory scoreboard tracks memory requests for each rank and bank of memory being addressed. When there are no pending requests, the scoreboard provides an indication to an idle timer that begins a count down to close a current page of the memory. The idle timer can be configured dynamically to close memory pages and to address dynamically-changing code streams by tracking previous decisions made on page closes.

Pending request scoreboard for out-of-order memory scheduler

A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

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Folsom, CA, United States of America

Suryaprasad Kareenahalli