Globalfoundries U.S. Inc.

Globalfoundries Inc.

Suryanarayana Kalaga

Sunil Kumar Singh

Xuan Anh Tran

Eswar Ramanathan

Juan Boon Tan

Hui Zang

Ajey Poovannummoottil Jacob

Robert Fox

Craig Child

Bala S Haran

Suresh Kumar Regonda

The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.

Vertical memory devices

One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.

Conductive structures for contacting a top electrode of an embedded memory device and methods of making such contact structures on an IC product

One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

Methods of forming a conductive contact structure to a top electrode of an embedded memory device on an IC product and a corresponding IC product

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor

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Mechanicville, NY, United States of America

Suryanarayana Kalaga