International Business Machines Corporation

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Infineon Technologies North America Corp.

Suryanarayan G Hegde

Omer H Dokumaci

Bruce Bennett Doris

Dureseti Chidambarrao

Helmut Horst Tews

Meikei Ieong

Erin C Jones

Oleg Gluschenkov

Rajarao Jammy

Johnathan E Faltermeier

Ulrike Gruening

Hiroyuki Akatsu

Kathryn Wilder Guarini

Rajesh Rengarajan

Yujun Li

Paul Andrew Ronsheim

Richard D Kaplan

Mukesh Vijay Khare

Brian S Lee

Jack Allan Mandelman

Carl John Radens

Timothy Joseph Chainer

Chandrasekhar Narayan

Emanuel Israel Cooper

Edward John Yarmchuk

Charles Hampton Perry

David W Albrecht

Kam Leung Lee

Anthony Paul Praino

Muthuthamby Sri-Jayantha

Dale Curtis McHerron

James William Berberich

Paul M Gaschke

Robert A Scranton

Mark R LaForce

Thomas Franklin Roth

Frederick L Taber, Jr

Steven J Root

Gobina Das

Omer H Dokumachi

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Self-aligned planar double-gate transistor structure

A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

Self-aligned planar double-gate process by self-aligned oxidation

The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETS, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

CMOS performance enhancement using localized voids and extended defects

The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

Self-aligned planar double-gate process by amorphization

The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

Orientation independent oxidation of nitrided silicon

A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm . The annealing process is preferably performed at temperatures in a range from about 550&deg; C. to about 1000&deg; C. and for a time period between about 1 second and about 2 hours.

Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation

A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.

Method of enhanced oxidation of MOS transistor gate corners

A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a < > crystal plane and a < > crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the < > crystal plane of the trench side wall, but not into the < > crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Process for fabricating a uniform gate oxide of a vertical transistor

Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.

Application of excimer laser anneal to DRAM processing

A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a &lt;100&gt; crystal plane and a &lt;110&gt; crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the &lt;110&gt; crystal plane of the trench side wall, but not into the &lt;100&gt; crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

A multiple-chip probe assembly suitable for wafer testing over a wide temperature range includes a plurality of individual buckling beam probe elements. A support structure supports the plurality of buckling beam probe elements in an arrangement in accordance with an electrical contact footprint for use in electrically contacting multiple chips of a wafer under test and enables buckling movement in a contacting direction of the plurality of buckling beams. The support structure includes a principal support material having a thermal coefficient of expansion (TCE) matched with the wafer under test and a second material other than the principal support material, wherein a contact positioning of the plurality of buckling beam probe elements upon the wafer under test during a testing operation is maintained. The second material prevents an individual probe element from electrically contacting the principal support material.

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Hollowville, NY, United States of America

Suryanarayan G Hegde