Freescale Semiconductor,inc.

Freescale Semiconductors Inc.

Surya Veeraraghavan

Mark Douglas Hall

Leo Mathew

Anis Mahmoud Jarrar

David Russell Tipple

Yang Du

Savithri Sundareswaran

Glenn O Workman

Lixin Ge

A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.

Systems and methods for reducing power consumption in semiconductor devices

An approach is provided in which a system executes transistor-level circuit simulation of a standard cell that includes parameters corresponding to a semiconductor manufacturing technology process. Sensitivity data is collected that quantifies changes to performance metrics corresponding to the standard cell in response to adjusting one or more of the parameters during the transistor-level circuit simulation. In turn, the system generates derate factors based upon the sensitivity data and tests an integrated circuit design according to the derate factors. Testing the integrated circuit design includes performing static timing analysis on the integrated circuit design that simulates operation of a device built from the integrated circuit design using the semiconductor technology process. In one embodiment, when the static timing analysis indicates timing violations, the system dynamically generates custom derate factors for particular cell instances corresponding to the timing violations. In turn, subsequent timing analysis is performed using the custom derate factors.

Timing margins for on-chip variations from sensitivity data

A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed

A method for forming a silicon-on-insulator transistor () includes forming an active region () overlying an insulating layer (), wherein a portion of the active region provides an intrinsic body region (). A body tie access region () is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode () is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion () of the body tie access region. The gate electrode is formed having a substantially constant gate length () along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes () are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion () is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

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Austin, TX, United States of America

Surya Veeraraghavan