Xilinx, Inc.

Surya Pratik Saha

Aman Gayasen

Kameshwar Chandrasekar

Ashish Sirasao

Elliott Delaye

Shangzhi Sun

Sumanta Datta

Manpreet Singh

Sanjay Saha

A circuit design is partitioned into a plurality of partitions during a first synthesis by a computer processor. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions. The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions, and the computer processor then combines the respective re-synthesized partitions and the unchanged partitions into a complete synthesized circuit design in a memory.

Optimization-aware incremental synthesis

Incremental synthesis for changes to a circuit design can include synthesizing, using computer hardware, a first circuit design resulting in a partitioning of the first circuit design and a plurality of synthesized partitions of the first circuit design and, for a second circuit design that is a modified version of the first circuit design and based upon the partitioning of the first circuit design, determining, using the computer hardware, a partition of the second circuit design that differs from the first circuit design. The partition of the second circuit design can be technology mapped using the computer hardware resulting in a synthesized partition of the second circuit design. A synthesized circuit design corresponding to the second circuit design can be generated using the computer hardware by combining synthesized partitions of the plurality of synthesized partitions of the first circuit design that are unchanged relative to the second circuit design with the synthesized partition of the second circuit design.

Incremental synthesis for changes to a circuit design

Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.

Parallelizing timing-based operations for circuit designs

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Hyderabad Telangana, India

Surya Pratik Saha