Brocade Communications Systems, Inc.

Brocade Communication Systems LLC

Vexata, Inc.

Surya Parkash Varanasi

Kung-Ling Ko

Timothy John Millet

Zahid S Hussain

John Michael Terry

Wing Cheung

Joseph Juh-En Cheng

Suresh Vobbilisetty

David Aaron Skirmont

Daniel Kiernan Kilkenny

Shailendra Jha

Parviz Ghalambor

Phanidhar Koganti

Anoop Ghanwani

Shunjia Yu

Prateek Sharma

Ramkumar Vadivelu

Vinodh Ravindran

Venkatesh Nagapudi

Satsheel Altekar

Tony Nguyen

Gregory S Walter

Indraneel Ghosh

Described is a redundant array of inexpensive disks (RAID) scheme that manages the wear of individual drives in a RAID set and significantly reduces the probability of more than two drives wearing out at the same time. In one aspect, describe is a method in which at least one of a first and second of the plurality of at least three low endurance flash based solid state devices perform a predetermined percentage of more writes as compared to at least a third of the plurality of at least three low endurance flash based solid state devices. In another aspect, a rebuild operation is performed using Galois Field Multiplication, with one of an integrated circuit and a field programmable gate array (FPGA) being used in preferred implementations.

Endurance aware raid scheme for flash based SSDS with FPGA optimized implementation

Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.

Input output scheduling for solid state media

Systems and techniques for processing and/or forwarding packets are described. An ingress switch can use a QoS mapping mechanism to map a first set of Quality of Service (QoS) bits in a packet received from a customer to a second set of QoS bits for use in a Transparent Interconnection of Lots of Links (TRILL) packet which encapsulates the packet. The first set of QoS bits can be different from the second set of QoS bits. The TRILL packet can be processed and/or forwarded in the network based on the second set of QoS bits. At the egress switch, the TRILL packet can be decapsulated and the original packet with the original QoS bits (or QoS bits that are different from the original QoS bits) can be forwarded to the customer's network. In this manner, some embodiments of the present invention can preserve the QoS bits across a TRILL network.

Preserving quality of service across trill networks

Described is an improved storage architecture. In a particular aspect an improved storage architecture with increased throughput to Ethernet storage modules due to elimination of data path handling from a main control CPU is set forth. Other method and apparatus are described therein, including a scalable Ethernet storage module particularly suited for usage with the improved storage architecture described herein.

Storage architecture for storage class memories

Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

Pluggable transceiver module with enhanced circuitry

One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

Method and system for link aggregation across multiple switches

Embodiments of methods, apparatuses and systems for balancing flow across trunk groups are disclosed. For example, a method of routing a flow of frames may include applying a correspondence between logical ports and physical ports of a switch. Other examples may include receiving at least one frame; selecting an exit port of a switch for the one frame to exit, based at least in part, on balancing flow across trunk groups; and transmitting the at least one frame.

Frame traffic balancing across trunk groups

A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

Host bus adapter with multiple hosts

Embodiments of methods, apparatuses and/or systems for balancing flow across trunk groups are disclosed. For example, a method of routing a flow of frames may include receiving at least one frame; selecting an exit port of a switch for the at least one frame to exit based, at least in part, on balancing flow across trunk groups; and transmitting the at least one frame.

Trunk groups being assigned logical port values, with multiple physical ports designated to form the given trunk group, thus corresponding to the logical port. This provides greater flexibility in developing trunk groups. Each trunk group delivers frames in order. Routing and balancing decisions are based on the logical port not the physical port.

Logical ports in trunking

Accordingly, there is disclosed herein an augmented Fibre Channel (FC) frame format which may provide support for multiple fabric FC networks, and may improve the performance of modularly-constructed switches. In one embodiment, the augmented FC frame format is modulated on a carrier signal and the frame includes: a start-of-frame field; a supplementary header field that follows the start-of-frame field; a frame header field that follows the supplementary header field; a cyclic redundancy code (CRC) checksum field; and an end-of-frame field that follows the CRC checksum field. The supplementary header field may include a destination tag that identifies a target fabric to which the frame is directed. Alternatively, or in addition, the supplementary header field may include an egress port identifier that identifies a switch port through which the frame is to exit a switch. The supplementary header may also include flags to request special handling by the receiver.

Supplementary header for multifabric and high port count switch support in a fibre channel network

Embodiments of methods, apparatuses and/or systems for routing a flow of frame in a core-edge switch configuration are disclosed. For example, a method of routing a flow of frames may include receiving at least one frame; selecting an exit port of a switch for the at least one frame to exit based, at least in part, on balancing frame traffic in the core-edge switch configuration; and transmitting the at least one frame.

Load balancing in core-edge configurations

The present invention provides a system and a method for filtering a plurality of frames sent between devices coupled to a fabric by Fiber Channel connections. Frames are reviewed against a set of individual frame filters. Each frame filter is associated with an action, and actions selected by filter matches are prioritized. Groups of devices are 'zoned' together and frame filtering ensures that restrictions placed upon communications between devices within the same zone are enforced. Zone group filtering is also used to prevent devices not within the same zone from communicating. Zoning may also be used to create LUN-level zones, protocol zones, and access control zones. In addition, individual frame filters may be created that reference selected portions of frame header or frame payload fields.

Growing community of inventors

Dublin, CA, United States of America

Surya Parkash Varanasi