International Business Machines Corporation

Suriya T Skariah

Arun Joseph

Rahul Rao

Arya Madhusoodanan

James Douglas Warnock

Sachin Gupta

Vasant B Rao

James E Sundquist

A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Cross-current power modelling using logic simulation

An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time. The information handling system compares the timing constraint sensitivity against a characterized sensitivity generated by a software modeling system and, when the timing constraint sensitivity does not match the characterized sensitivity, one or more of the software modeling system's modeling parameters are adjusted, causing the software modeling system to generate a changed characterized sensitivity of the circuit model.

Validating variation of timing constraint measurements

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Kochi, India

Suriya T Skariah