Stmicroelectronics International N.v.

Stmicroelectronics S.r.l.

Surinder Pal Singh

Giuseppe Desoli

Thomas Boesch

Nitin Chawla

Kaushik Saha

Anuj Grover

Manuj Ayodhyawasi

Carmine Cappetta

Sumit Johar

Aneesh Bhasin

Saumya Suneja

Elio Guidetti

Fabio Giuseppe De Ambroggi

Paolo Zambotti

Tommaso Majo

A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

Tagged memory operated at lower VMIN in error tolerant system

A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

Neural network hardware accelerator circuit with requantization circuits

An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.

Arithmetic unit for deep learning acceleration

Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

Deep convolutional network heterogeneous architecture

A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

Data volume sculptor for deep learning acceleration

Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

Variable clock adaptation in neural network processors

Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks

Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.

Convolution acceleration with embedded vector decompression

Tagged memory operated at lower vmin in error tolerant system

A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

Streaming access memory device, system and method

A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

Pooling unit for deep learning acceleration

Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.

Acceleration unit for a deep learning engine

A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit, and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has a plurality of inputs and at least one output, and the arithmetic unit is solely dedicated to performance of a plurality of parallel operations. Each one of the plurality of parallel operations carries out a portion of the formula: output=AX+BY+C.

Growing community of inventors

Noida, India

Surinder Pal Singh