Texas Instruments Corporation

Suribhotla Rajasekhar

Ross Eliot Teggatz

Reed Wilburn Adams

Marco Corsi

David John Baldwin

Jingwei Xu

Robert J Landers

Thomas A Schmidt

Tobin D Hagan

William E Grose

Hasibur Rahman

Kenneth George MacLean

Karthik Vasanth

Alexander Noam Teutsch

Ismail Hakki Oguzman

Sanmukh Makan Patel

Rex M Teggatz

Valerian Mayega

Tri Cao Nguyen

Arash Loloee

Kee-Chee Tiew

Jonne J Sebastian Lindeberg

An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter output driver and a first transmitter input driver. The first transmitter output driver includes an N-type device serially coupled to a P-type device. The first transmitter input driver includes an N-type device serially coupled to a P-type device. An output of the first transmitter input driver is coupled to an input of the first transmitter output driver. The first transmitter output driver drives an output of the transmitter to a first voltage and the first transmitter input driver drives the output of the transmitter to a second voltage while the first transmitter output driver is disabled.

High voltage ultrasound transmitter with gate protection diodes and intrinsic output zeroing

A system and method are disclosed for capturing pre- and post-event data for random events using minimum power. Real-time data is captured and stored in a continuous loop in a segment of a first memory. Upon detection of a designated event, a second memory is powered-on and post-event data is stored to a segment of the second memory. After a designated data capture window, the second memory is powered-off and real-time data is captured in an unused segment of the first memory. The post-event data may be captured in the unused segment of the first memory and later transferred to the second memory. Auto-address logic monitors and controls the storage and retrieval of pre- and post-event in the first and second memory. An energy management system determines and controls which segments of the first and second memory should be powered-on or kept in the stasis mode to store event data.

Low-power data loop recorder

In accordance with an aspect of the present invention, an LED driving circuit includes a digital-to-analog converter and a driving portion. The circuit is operable to turn off the digital-to-analog converter at times when the driving portion is not providing a high signal. As such the digital-to-analog converter will waste less energy.

Dynamic power saving pulse width modulated LED driver circuit

A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.

Bidirectional deglitch circuit

In a method and system for controlling a direct current to direct current (DC-DC) converter includes an inductor coupled to receive a voltage input at an input terminal. A diode is coupled in series between the inductor and an output terminal of the DC-DC converter. A switch is coupled between the inductor and a ground reference. The switch receives a control signal from a controller for adjusting a duty cycle of the DC-DC converter. The duty cycle controls an output voltage at the output terminal. The controller generates the control signal in response to receiving a feedback signal, which is derived as a predefined function of a voltage feedback signal indicative of the output voltage and a current feedback signal indicative of a current flowing through the inductor.

Self-oscillating boost DC-DC converters with current feedback and digital control algorithm

A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

Current limiting circuit for high-speed low-side driver outputs

A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition. In a second mode of operation, independent node control circuit includes a second control signal input that is operable to couple to the output terminal of the error amplifier while simultaneously the first power supply rail is operable to couple to the output terminal of the voltage regulator to provide double power density.

Programmable voltage regulator configurable for double power density and reverse blocking

A bias device that modifies the bias of a device based on an input signal to the device. The device may have a fixed bias, and the bias device can be connected in parallel with the fixed bias. The device can be an amplifier, such as a linear amplifier or a class AB amplifier. The bias device can be configured to provide maximum bias during the device's crossover time period.

Bias system and method

The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure () that comprises a first transistor (), having a first terminal coupled to ground, a second terminal coupled to a control signal (), and a third terminal coupled to a first end of a first resistive element (). A first voltage source () is coupled to the second end of the first resistive element. A second resistive element () is intercoupled between the second end of the first resistive element and ground. A second transistor () has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (). A third resistive element () is intercoupled between the third terminal of the second transistor and ground; and a third transistor () has a first terminal coupled () to the oxide structure, a second terminal coupled to the first end of the first resistive elerment, and a third terminal coupled to a second voltage source ().

Growing community of inventors

Plano, TX, United States of America

Suribhotla Rajasekhar