Poet Technologies, Inc.

Globalfoundries Inc.

Motorola Corporation

Other

Freescale Semiconductor,inc.

Globalfoundries U.S. Inc.

Suresh Venkatesan

Mahbub Rashed

Subramani Kengeri

Yee Loy Lam

Miroslaw Florjanczyk

Irene Y Lin

Marc Laurent Tarabbia

Chinh Nguyen

Jing Yang

Yunfei Deng

William Ring

Jeff Kim

Jongwook Kye

Scott C Johnson

Steven R Soss

Mohammed Rabiul Islam

David Doman

Trevor Hall

Yuansheng Ma

Brian George Anthony

Lucas Soldano

Peng Liu

Marius K Orlowski

Jason Eugene Stephens

Juhan Kim

Janos Farkas

Venkat Kolagunta

Stephen S Poon

Rajesh Tiwari

John Mendonca

Rod Augur

Abbas Guvenilir

Srikanth Balaji Samavedam

Shibly S Ahmed

Navneet Jain

Long Cheng Koh

Yong M Lee

Seung-Hyun Rhee

Yuan Lei

Loy Yee Lam

Jeffrey Lutze

Dinesh Somasekhar

Yan E Wang

Ali Keshavarzi

James David Burnett

Olubunmi O Adetutu

Douglas Michael Reber

Lei Yuan

William James Taylor, Jr

Jon T Fitch

Roderick Alan Augur

Alexander Barr

Keith E Witek

Michael D Turner

Kurt H Junker

Bradley Paul Smith

Christopher C Hobbs

Sergio A Ajuria

Rode R Mora

John M Grant

Stuart E Greer

Toni D Van Gompel

Ramnath Venkatraman

David Clegg

Asanga H Perera

John J Hackenberg

Ingolf Lorenz

Bradley P Smith

Gregor Braeckelmann

James B Gullette

Stephen R Crown

Rebecca G Cole

Jongwook K E

Xiang Qi

Jeffrey S Cope

Brad Smith

Veena Misra

Earnest B Wilson

Scott Johnson

Yong Meng Lee

Steve Soss

Larry Ho

James Benjamin Gullette

A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.

Optical dielectric planar waveguide process

A structure and method for the wafer level testing of interposer-based photonic integrated circuits is described that includes the formation of an upturned mirror structure and the method of utilizing the interposer-based mirror structure for electrical and optical testing of optoelectrical circuits that include emitting components such as lasers, detecting components such as photodetectors, and both emitting and detecting components. Electrical activation of the optoelectrical emitting or sending devices and the subsequent detection and measurement of the optical signals in detecting or receiving devices provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.

Structure and method for testing of PIC with an upturned mirror

Alignment aid structures and the method of formation of these structures on an interposer comprised of a planar waveguide layer and a base structure, facilitate the alignment of the optical axes of optical and optoelectrical devices formed from and mounted to the interposer. Alignment aids formed from a common hard mask on the planar waveguide layer of the interposer structure include vertical and lateral alignment structures and fiducials. Optical losses for signals propagating in interposer-based photonic integrated circuits are reduced with effective alignment structures and methods.

Self-aligned structure and method on interposer-based PIC

Embodiments of alignment structures are disclosed that enable the alignment of a fiber attach unit (FAU) and the optical fibers contained therein to optical components on optical interposers or substrates on which photonic integrated circuits (PICs) are formed. Alignment of the optical fibers is enabled without the requirement for powering of the active optoelectrical devices in the PIC, but rather use an external testing apparatus to provide one or more optical signals to facilitate alignment. Methods for alignment using embodiments of the alignment structure is also disclosed.

Fiber block alignment structure

A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.

Loopback waveguide

A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

Semiconductor device with transistor local interconnects

An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.

Optical dielectric waveguide subassembly structures

A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.

Method of forming an hermetic seal on electronic and optoelectronic packages

The invention described herein pertains to the structure and formation of an optical device that includes a planar laser and a waveguide. The planar laser has a large lateral QW-containing layer and a tapered section in a transition portion of the device structure that enable low diode leakage currents and facilitate transition of the optical signal from the laser to a transition waveguide, and in some embodiments, to a dilute waveguide.

Planar laser structure with vertical signal transition

Growing community of inventors

Danbury, CT, United States of America

Suresh Venkatesan