Intel Corporation

Qualcomm Incorporated

Suresh Sugumar

Baskaran Ganesan

Ned M Smith

Vedvyas Shanbhogue

Devadatta V Bodas

Russell Jerome Fenger

James Steven Burns

Kiran Singh Panesar

Sundaravarathan R Iyengar

Sanjay Bakshi

Tessil Thomas

Sridhar Muthrasanallur

Gunner D Danneels

Feranak Nelson

John M Powell, Jr

Mahesh K Kumashikar

Rahul Pal

Rajat Mittal

Jeffrey Gemar

Ali Taha

Dheemanth Nagaraj

Amy Derbyshire

Sudeep Divakaran

Tao Xue

Trang Nguyen

Mohammad Tamjidi

Vishwanath Somayaji

Vijayanand Naik

Narayan N Iyer

Methods and apparatus for implementing a low-pin count architecture with priority message arbitration and delivery. The architecture includes a hardware-based message arbitration unit (MAU) including a plurality of priority queues, each having a respective priority level, implemented on a first component, such as a processor and/or System on a Chip (SoC). The first component is communicatively coupled to a second component via a low-pin count link such as an I2C bus. The MAU receives prioritized messages from clients and enqueues the messages in priority queues based on their priority levels. An arbiter selects messages to transmit over the low-pin count link from the priority queues. The MAU further may abort transmission of a message in favor of transmission of a higher-priority message to guarantee a transmit latency. Under one implementation, the components are a processor and a PMIC configured to communicate with a USB Type-C power source and meet timing requirements defined by a USB Power Delivery Specification.

Low pin-count architecture with prioritized message arbitration and delivery

Aspects of an apparatus are disclosed. The apparatus is configured to receive power from any number of power sources. The apparatus includes a load and a power management. The power management circuit is configured to manage power supplied by the power source to the load. The load is dynamically configurable to operate within the current capability of the power source.

Dynamically configurable apparatus for operating within the current capabilities of the power source

An apparatus is provided. The apparatus includes a plurality of cores and a temperature sensor configured to monitor a temperature for the cores. The apparatus further includes t least one switch, each being configured to supply power to one of the cores. A thermal mitigation module is configured to operate the at least one switch at a duty cycle based on the monitored temperature. A method for thermal mitigation for an apparatus is provided. The method includes monitoring a temperature for a plurality of cores, supplying power to one of the cores at a duty cycle, and adjusting the duty cycle based on the monitored temperature. Another apparatus is provided. The apparatus includes a plurality of cores, means for monitoring a temperature for the cores, means for supplying power to one of the cores at a duty cycle, and means for adjusting the duty cycle based on the monitored temperature.

Thermal mitigation with power duty cycle

An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Processor power management responsive to a sequence of an instruction stream

A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn signal is sent over a dedicated wake-warn channel to indicate to the system component that the request is to arrive. Wake-warn signals cause a disabled clock to be ungated to an enabled state. The request is then sent to the system component.

Early wake-warn for clock gating control

A manageability engine or adjunct processor on a computer platform may receive a request for activation and use of features embedded within that platform from a service provider authorized by the manageability engine's manufacturer. The manageability engine may initiate a request for authority through the service provider to a permit server. The permit server may provide, through the service provider, proof of the service provider's authority, together with a certificate identifying the service provider. Then the manageability engine may enable activation of the features on the platform coupled to the manageability engine, but only by the one particular service provider who has been authorized.

Dynamic platform reconfiguration by multi-tenant service providers

In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Increasing power efficiency of turbo mode operation in a processor

Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

Efficient frequency boost operation

Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions. Embodiments of the invention may detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards a memory unit, a processor core executing a processor low-power mode, and a processor socket executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit and various components of the memory subsystem.

Memory link power management

Methods, systems and apparatuses to dynamically balance execution loads on a partitioned system among processor cores or among partitions.

Method for dynamic load balancing on partitioned systems

Embodiments of apparatuses, methods, and systems for guest to host address translations for devices to access memory in a partitioned system are disclosed. In one embodiment, an apparatus includes an interface, partitioning logic, first address translation logic, and second address translation logic. The interface is to receive a request from a device to access memory in a partitioned system. The partitioning logic is to determine whether the device is assigned to a first partition or a second partition. The first address translation logic is to translate a first guest address to a first host address in the first partition. The second address translation logic is to translate a second guest address to a second host address in the second partition.

Growing community of inventors

Bengaluru, India

Suresh Sugumar