Intel Corporation

Suresh Srinivas

Koichi Yamada

Jayaram Bobba

Quinn Able Jacobson

Matthew C Merten

Ruchira Sasanka

Kshitij Arun Doshi

Hong Wang

Per H Hammarlund

Gad Shlomo Sheaffer

David J Sager

Mingqiu Sun

John P Shen

Jeffrey J Cook

Omar M Shaikh

Anne Weinberger Bracy

Ali-Reza Adl-Tabatabai

Youfeng Wu

Bratin Saha

Gautham N Chinya

Ron Gabor

Konrad K Lai

Joseph Nuzman

Ravi Rajwar

Shlomo Raikin

Paul Caprioli

Tin-Fook Ngai

Sebastian Winkel

Abhay Kanhere

Ho-Seop Kim

Leeor Peled

Uma Srinivasan

Howard Chen

Stephen H Dohrmann

James E Smith

Abhinav Das

Jason A Domer

Yun Yu Wang

Ravishankar Iyer

Li Zhao

Donald K Newell

Rameshkumar G Illikkal

Arvind Krishnaswamy

Michael R Greenfield

Niranjan Hasabnis

Muawya M Al-Otoom

Ali-Reza Adi-Tabatabai

Miaobo Chen

Vivek Thakkar

Eric Lin

Suriya Madras-Subramanian

Jeffery J Cook

Gautham Shinya

Pawel Osciak

Chris Elford

Carl Lebsack

Bratin Saba

Abhay S Kanhere

Anne C Bracy

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

An inter-architecture compatibility apparatus of an aspect includes a control flow transfer reception module to receive a first call procedure operation, intended for a first architecture library module, from a first architecture code module. The first call procedure operation involves a first plurality of input parameters. An application binary interface (ABI) change module is coupled with the control flow transfer reception module. The ABI change module makes ABI changes to convert the first call procedure operation involving the first plurality of input parameters to a corresponding second call procedure operation involving a second plurality of input parameters. The second call procedure operation is compatible with a second architecture library module. A control flow transfer output module is coupled with the ABI change module. The control flow transfer output module provides the second call procedure operation to the second architecture library module.

Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture

A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Hardware profiling mechanism to enable page level automatic binary translation

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code

A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.

Instruction and logic to perform dynamic binary translation

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.

Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data ('SIMD') instructions.

Analyzing potential benefits of vectorization

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.

Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment

A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Technique for using memory attributes

In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment

In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to indicate the identity of the first agent, and storing the first identifier with the data in the cache line and updating at least one of a plurality of counters associated with the first agent in a metadata storage in the cache, where the counter includes information regarding inter-agent interaction with respect to the cache line. Other embodiments are described and claimed.

Providing application-level information for use in cache management

Growing community of inventors

Portland, OR, United States of America

Suresh Srinivas