Intel Corporation

Other

Suresh S Chittor

Rajat Agarwal

Rajee S Ram

Debendra Das Sharma

Mohan J Kumar

Wei P Chen

Robert G Blankenship

Sujoy Sen

Kai Cheng

Kenneth C Creta

James W Alexander

Akhilesh Kumar

Lily Pao Looi

Brian S Morris

Michelle C Jen

Sin Sim Tan

Phanindra Mannava

Dennis W Brzezinski

Kiran A Padwekar

Ching-Tsun Chou

Balint Fleischer

Vivek Joy Kozhikkottu

Chih-Cheh Chen

Shankar Ganesh Ramasubramanian

Jonathan Nick Spitz

Srinand Venkatesan

Esha Choukse

Andalib Khan

George Vergis

Linda J Rankin

Richard J Greco

Suneeta Sah

Douglas Heymann

Henk G Neefs

Wayne D Smith

Suvansh Krishan Kapur

David R Jackson

Prantik K Nag

Melin Dadual

David W Archer

Jim Sutton

Joseph Ku

Don Breazeal

A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

Sharing memory and I/O services between nodes

An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.

Memory utilized as both system memory and near memory

Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

Method and apparatus to reduce power consumption for refresh of memory devices on a memory module

Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.

Techniques for setting a 2-level auto-close timer to access a memory device

In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

System, apparatus and method for application specific address mapping

A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.

Link level retry scheme

Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

Mitigating silent data corruption in a buffered memory module architecture

Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

Silent data corruption mitigation using error correction code with embedded signaling fault detection

A system for carrying two channels of data over a single physical connection. In multi-node systems, data packets are divided into flits with flits from two channels being interleaved and carried by a single physical connection. Once the flits are transmitted, they are reassembled into packets in order to be carried by a processor bus. Controllers for the channel communicate to minimize 'bubbles' observed during packet assembly by the processor bus. Thus, the data is transferred in two different types of resource sharing paradigms.

System for sharing channels by interleaving flits

Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

Coherent variable length reads from system memory

A method and apparatus for third party agent transaction deferral on a host bus. A host bus transaction request is received from a device, and transaction information related to the transaction request is stored in an out of order queue. An indication is received from the third party agent that the transaction has been deferred, and the stored transaction information is updated to reflect that the transaction has been deferred.

Method and apparatus for deferring transactions on a host bus having a third party agent

A method and apparatus of selectively flushing a conflicted write transaction from a memory controller. According to the method, a new transaction is received that identifies a memory address to which the transaction is directed. It is determined whether an address of the new transaction matches an address of any previously queued transaction. When a match occurs, the one previously queued transaction that matches the new transaction is flushed from queue.

Selective conflict write flush

Coherent variable length reads which implicates multiple cache lines by

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Beaverton, OR, United States of America

Suresh S Chittor