Micron Technology Incorporated

Ferro Corporation

Suresh Ramarajan

Witold Kula

Manzar Siddik

Whonchee Lee

Wei Chen

Lifang Xu

Matthew J King

Kunal Shrotri

Jonathan D Harms

Jivaan Kishore Jhothiraman

Gowrisankar Damarla

Sri Sai Sivakumar Vegunta

Rithu K Bhonsle

John B Matovu

Rutuparna Narulkar

David S Meyaard

Kevin R Gast

Shashank Saraf

Yongjun Jeff Hu

David A Kewley

Robert J Hanson

Suryadevara Vijayakumar Babu

Daniel Billingsley

Xiaosong Zhang

Yie-Shein Her

Ramanathan Srinivasan

Keen Wah Chow

Biow Hiem Ong

Michael J Irwin

Md Zahid Hossain

Johnathan D Harms

An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

Apparatus and memory device including conductive lines and contacts, and methods of forming an apparatus including conductive lines and contacts

Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices

A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

Stair step structures including insulative materials, and related devices

A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoFeBwhere 'x' is from 0 to 90, 'y' is from 10 to 90, and &#x201c;z&#x201d; is from 10 to 50. The CoFeBis directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

Magnetic tunnel junctions

Semiconductor devices including a stair step structure, and related methods

A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm &#x3bc;m. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.

Methods of forming semiconductor devices including tunnel barrier materials

A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoFeBwhere 'x' is from 0 to 90, 'y' is from 10 to 90, and 'z' is from 10 to 50. The CoFeBis directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

Methods of forming semiconductor structures having stair step structures

Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.

Electroplating systems

Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for conditioning a polishing pad includes a member having a first surface and a plurality of contact elements projecting from the first surface. The member also includes a plurality of apertures configured to flow conditioning solution to the polishing pad. The apertures can extend from the first surface to a second surface opposite the first surface. The member can further include a manifold that is in fluid communication with the apertures. In another embodiment, a conditioner for conditioning the polishing pad includes an arm having at least one spray nozzle configured to spray conditioning solution onto the polishing pad and an end effector coupled to the arm. The end effector includes a first surface and a plurality of contact elements projecting from the first surface.

Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces

A method of selectively depositing metal features on a conductive surface of a substrate. An electrode assembly that includes a plurality of electrodes connected in series so as to be oppositely polarized when a voltage is applied thereacross is positioned over the conductive surface of the substrate. The plurality of electrodes is in close proximity to, but does not contact, the conductive surface of the substrate. Positively charged portions and negatively charged portions of the conductive surface of the substrate are created and metal ions are deposited on the negatively charged portions.

Noncontact localized electrochemical deposition of metal thin films

Growing community of inventors

Boise, ID, United States of America

Suresh Ramarajan