Qualcomm Incorporated

Suresh Naidu Lekkala

Sajin Mohamad

Chulkyu Lee

Darshan Chandrashekhar Pande

In certain aspects, a voltage regulator includes a pass transistor coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The voltage regulator also includes a voltage booster coupled between the output of the amplifier and a gate of the pass transistor. In certain aspects, the voltage booster includes a first capacitor and a second capacitor for double charge pumping. In certain aspects, a control circuit of the voltage booster is coupled to a voltage source that is independent of an output voltage of the amplifier.

Charge pump based low dropout regulator

A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.

Bandwidth enhanced amplifier for high frequency CML to CMOS conversion

Certain aspects of the present disclosure generally relate to a sampling circuit, such as a sampling circuit for a low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) system. One example sampling circuit generally includes a latching circuit and a plurality of pass-gate transistors. The latching circuit includes differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit. Each pass-gate transistor is coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit.

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Bengaluru, India

Suresh Naidu Lekkala