Intel Corporation

Intel Ndtm US LLC

Suresh Nagarajan

Shankar Natarajan

Sriram Natarajan

Romesh B Trivedi

Arun Sitaram Athreya

Yihua Zhang

Anoop Mukker

Ramkarthik Ganesan

Aliasgar S Madraswala

Sahar Khalili

Jason B Akers

Shivashekar Muralishankar

Neil A Gabriel

Scott Crippin

Vinod K Puvvada

Dale Craig Barfuss

Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

Power and thermal management in a solid state drive

In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Techniques for preventing read disturb in NAND memory

A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

Logical to physical address indirection table in a persistent memory in a solid state drive

Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

Host managed buffer to store a logical-to physical address table for a solid state drive

Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

Utilizing NAND buffer for DRAM-less multilevel cell programming

Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.

Method and apparatus to improve write bandwidth of a block-based multi-level cell nonvolatile memory

An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

Dynamic single level cell memory controller

An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.

Method to improve mixed workload performance on storage devices that use cached operations

An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.

Mass storage device with host initiated buffer flushing

Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Block management for dynamic single-level cell buffers in storage devices

Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.

Host managed solid state drivecaching using dynamic write acceleration

According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory.

Use of a shutdown object to improve initialization performance

Logical units of allocation may be designated as overhead and unallocated and made unavailable for use. During one or more write operations, when one or more logical unit is invalidated, one or more of the unallocated overhead logical units may be designated as available for use and one or more of the invalidated logical units may be designated as overhead.

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Folsom, CA, United States of America

Suresh Nagarajan