Intel Corporation

Other

Zenith Data Systems Corporation

Packard Bell Nec

Suresh K Marisetty

Mani Ayyar

Koichi Yamada

Scott D Brenden

Andrew J Fish

William S Wu

Kushagra V Vaid

Puthiya K Nizar

Norman J Rasmussen

George Thangadurai

Rajendra Kuramkote

Mohan J Kumar

Shivnandan D Kaushik

Nhon Toai Quach

Thomas F Joyce

Jian-Kuo Shen

Jose Andy Vargas

Chester M Nibby, Jr

Bruno DiPlacido, Jr

Jeffrey S Somers

Thomas L Murray, Jr

Bernard Lint

Michelle A Pence

James F Bertone

G Lewis Steiner

Lance J McNally

Martin Massucci

Marc Sanfacon

Murugasamy K Nachimuthu

James P Kardach

James B Crossland

Krishnan Ravichandran

Sham M Datta

Yan Li

Baskaran Ganesan

Gautam Doshi

Eshwari Prasad Komarla

Amy L O'Donnell

Graham D Kirby

William Cheung

Yaron Shragai

Jim B Crossland

Stan Domen

Sriram Visvanathan

Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

System abstraction layer, processor abstraction layer, and operating system error handling

Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.

Method and apparatus for redirection of machine check interrupts in multithreaded systems

A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call and a seed mode call. When a query mode call is issued, it may request whether or not the system firmware and hardware support the injection of a specified kind of error. A return from this call may be used to make a list of supported errors for injection. When a seed mode call is issued, the corresponding error may be injected into the hardware.

System and method for error injection using a flexible program interface field

Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

OS and firmware coordinated error handling using transparent firmware intercept and firmware services

Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Configurable error handling apparatus and methods to operate the same

A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Error correction apparatus, systems, and methods

Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.

Poisoned error signaling for proactive OS recovery

A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.

Method and apparatus for handling errors in a processing system

A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMV&#xd7;D) responsible for performing idle detection for devices. The PMV&#xd7;D performs idle detection using event timers that provide an indicator as to the activity level. The PMV&#xd7;D places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.

Method and apparatus for adjusting a power consumption level based on the amount of time a processor clock is stopped

A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.

Scalable CPU error recorder

Method and apparatus for reducing power consumption in a system using power management software capable of placing multiple configurable system devices in a reduced power consumption state

Algorithm for non-volatile memory updates

Rendezvous of processors with OS coordination

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Symmetric multiprocessing system with unified environment and

Growing community of inventors

San Jose, CA, United States of America

Suresh K Marisetty