Amazon Technologies, Inc.

Ip-first, LLC

Suresh Hariharan

Kun Xu

James R Lundberg

Stanley Ho

To generate sequential addresses when multiple integrated circuit (IC) devices are accessing the same memory, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token is first transferred along the ring topology during a memory reservation phase in which each IC device can set a corresponding memory request bit to indicate that the IC device has data to write to the memory. The modified address token is then transferred along the ring topology again during a memory access phase. During the memory access phase, each IC device that has data to write can perform a memory write operation using a sequential address determined from the contents of the address token.

Address generation for page collision prevention

To generate sequential addresses when multiple integrated circuit (IC) devices are accessing a memory region, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token includes a data increment value for the memory region. When a device receives the address token, a memory write address is determined based on the data increment value and a base address corresponding to the memory region for the current write cycle. The IC device can perform a write operation using the memory write address if the device has data to write. The data increment value of the address token is then updated based on the number of data units being written in the current write cycle to the memory region by the IC device, and the updated address token is transmitted to the next IC device of the ring topology.

Address generation for page collision prevention in memory regions

An IC including skew-programmable clock buffers, fixed skew logic circuit, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed logic circuit enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic circuit is implemented as any type of permanent programmable block, such as laser-blown fuses, an EPROM, etc.

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Austin, TX, United States of America

Suresh Hariharan