Alcatel Lucent

Lucent Technologies Inc.

Alcatel-lucent USA Inc.

University of Limerick

Suresh Goyal

Alexei Ashikhmin

Michele Portolan

Chen-Huan Chiang

Sanjay Sudhaker Upasani

Pratod V Kasbekar

Harish S Mangrulkar

Katherine Hua Guo

Thomas L Marzetta

Bradford Van Treuren

Tapan J Chakraborty

Yigal Bejerano

Dusan Suvakovic

Steven K Korotky

Lester Tse Wee Ho

Eugene J Rosenthal

Oliver Blume

Rajarshi Ray

Gary Weldon Atkinson

Daniel Charles Kilper

Hong Yang

George Endicott Rittenhouse

Frank William Sinden

John Edward Clarke

Jeff Punch

Francesco Cottone

Marie-Loic Leport

Edward K Buratynski

Elliot N Pinson

Bryan Anthony Rodgers

Holger Claussen

Bradford G Van Treuren

Bradford Gene Van Treuren

Tapan Jyoti Chakraborty

Louis Gwyn Samuel

A system and method for analyzing network power consumption is disclosed. The system and method for analyzing network power consumption includes the steps of specifying at least one service which will run on said network; defining a plurality of resources provisioned in the network, each having an associated power efficiency; associating a network path with the service; calculating a sum of the power efficiencies for the resources of the network path; and outputting the sum to a display device. The system and method for analyzing network power consumption is particularly useful for identifying power consumption efficiencies throughout a communication network.

System and method for analyzing network power consumption

A system and method for dynamically modifying scheduling of scan operations for a system under test includes a processing module configured to apply input test data to the system under test based on the scan operations via a test access port and a scheduler adapted to provide the processing module with scheduling for the plurality of scan operations. The scheduler includes a circuit model of the system under test. The circuit model includes at least one attribute providing enhancing information for at least a portion of the system under test. The scheduler is adapted to schedule the scan operations based on the circuit model and to modify the schedule based on the at least one attribute. The processing module is configured to receive the modified scheduled scan operations and to apply the input test data to the system under test based on the modified scheduled scan operations.

Systems and methods for dynamic scan scheduling

Various methods and devices are provided to address the need for improved multicast operation. In one method, a feedback mobile device receives (), from a multicast sender, a multicast transmission for a plurality of mobile devices, the plurality of mobile devices further including a group of non-feedback mobile devices. The feedback mobile device transmits () an indication of feedback mobile channel quality observed by the feedback mobile device to the multicast sender and to the group of non-feedback mobile devices. The feedback mobile device receives () from at least one non-feedback mobile device, an indication of non-feedback mobile channel quality at the at least one non-feedback mobile device and transmits () an indication of the non-feedback mobile channel quality to the multicast sender and to the group of non-feedback mobile devices.

Method and apparatus for improved multicast service using negotiated feedback

A position-based scheduling capability supports interaction between one or more user applications and a scheduler for performing testing via a scan chain of a unit under test. The scheduler receives access requests from one or more user applications, where each access request is a request for access to a segment of the scan chain, respectively. The scheduler determines scheduling of the access requests using a circuit model configured to represent an ordering of the segments of the scan chain. The scheduler may provide the access responses to the user application(s) from which the access requests are received, thereby enabling the user application(s) to issue test operations toward a processor configured to generate test data to be applied to the scan chain. The scheduler may obtain the test operations and send the test operations toward a processor configured to generate test data to be applied to the scan chain.

Method and apparatus for position-based scheduling for JTAG systems

A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

Method and apparatus for deferred scheduling for JTAG systems

An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.

Method and apparatus for system testing using multiple processors

A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches). The Virtual ICE Driver is configured for receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and providing the scheduled set of scan segment operations to a processor configured for executing the scheduled set of scan segment operations for testing the target hardware.

Method and apparatus for virtual in-circuit emulation

An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP) is provided. The apparatus includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP. The set of instructions of the test instruction set architecture includes a first set of instructions including a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of instructions including a plurality of test instructions associated with the TAP. The instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form the set of instructions of the test instruction set architecture.

Method and apparatus for system testing using multiple instruction types

A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior to deployment or sale of the system, in-field testing after deployment or sale of the system, in-field modification of the system, and the like. The scan chain security capability enables secure control over normal use of a scan chain by enabling control over interruption of a scan chain and re-establishment of an interrupted scan chain. A scan chain security component is configured for removing an open-circuit condition from the scan chain in response to a control signal. The control signal may be generated in response to validation of a security key, in response to successful completion of a challenge-based authentication process, or in response to any other suitable validation or authentication. The scan chain security component also may be configured for creating an open-circuit condition in the scan chain in response to a second control signal. The second control signal may be a scan register value received via the scan chain.

Method and apparatus for providing scan chain security

An improved vibrational energy harvester includes a housing and at least one energy transducer. In an embodiment, a second mass element is arranged to receive collisionally transferred kinetic energy from a first mass element when the housing is in an effective state of mechanical agitation, resulting in relative motion between the housing and at least one of the second and further mass elements. The energy transducer is arranged to be activated by the resulting relative motion between the housing and at least one of the second and further mass elements. In a further embodiment, kinetic energy is collisionally transferred in a velocity-multiplying arrangement from the first to a second or further mass element that has a range of linear ballistic motion. The energy transducer is arranged to be activated, at least in part, by the ballistic motion of the second or further mass element. The energy transducer, or a portion of it, may be attached to the housing, or it may be attached to another of the mass elements.

Energy harvester apparatus having improved efficiency

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing

The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level.

Apparatus and method for isolating portions of a scan path of a system-on-chip

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Method and apparatus for describing and testing a system-on-chip

The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

Apparatus and method for controlling dynamic modification of a scan path

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Growing community of inventors

Warren, NJ, United States of America

Suresh Goyal