International Business Machines Corporation

Other

Suresh Eswara Warrier

Bruce Gerard Mealey

Luke Matthew Browning

Kenneth Bernard Rozendal

Mysore Sathyanaranyana Srinivas

Dean J Burdick

Michael Gerard Mall

Greg Robert Mewhinney

James Bernard Moody

Giles R Frazier

Randal Craig Swanberg

Christopher Francois

Balamurugan Ramajeyam

Muthulakshmi Pearl Srinivasan

Parag S Patel

Avinash Srikrishna Chinchalkar

Malik Magdon-Ismail

An operating system interface, responsive to detecting a non-privileged thread request with a scheduling attribute set to a critical setting to request access to at least one privileged core, selectively schedules the non-privileged thread request into a privileged core queue associated with the at least one privileged core only when a resource availability of the at least one privileged class core meets a threshold level of availability, the at least one privileged core providing a higher throughput than at least one regular core. The operating system interface, responsive to detecting a privileged thread request with the scheduling attribute set to the critical setting, automatically scheduling the privileged thread request into the privileged core queue.

Efficient critical thread scheduling for non-privileged thread requests

Efficient critical thread scheduling for non privileged thread requests

A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

Low latency scheduling on simultaneous multi-threading cores

A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.

Time-based task priority boost management using boost register values

A method of generating consumer data by facilitating the communication of feedback in a group setting over a global data communications network is shown. After creating or joining a group, members of the group may send or receive polls, consisting of photos, videos, group texts and event messages to other group members and/or the poll creators' social networks. Other group members and social network friends are notified instantly or almost instantly and respond back promptly. The results are organized and presented in an engaging visual manner and the consumer data collected from such interactions are stored in a database.

Method and system of generating consumer data by facilitating the communication of feedback in a group setting

A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.

Offloading input/output (I/O) completion operations

An approach to profiling software programs that uses a small pinned buffer and a large unpinned histogram buffer is presented. When a process that is being profiled receives a time slice, the process' program counter is written to the small pinned buffer by a kernel routine. The small pinned buffer is configured to be large enough to store several program counters. When the small pinned buffer is full, or almost full, an internal profiling signal is sent by the kernel routine. When the process is resumed, any outstanding signals are processed before resuming the process. The profiling signal is handled by reading the program counters from the small pinned buffer, calculating a slot in the histogram buffer that corresponds to each of the program counters, incrementing the value in the corresponding histogram slots, and clearing the small pinned buffer so that it can be reused.

Scalable and improved profiling of software programs

A kernel of a SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors.

Managing execution of mixed workloads in a simultaneous multi-threaded (SMT) enabled system

A computer implemented method, a computer program product, and a data processing system trace information about current context and system state for either 32-bit or 64-bit applications. A 32-bit trace executable code and a 64-bit trace executable code are compiled for a trace script. A determination is then made as to whether an application process is a 32-bit process or a 64-bit process. Responsive to determining that the application process is the 32-bit process or the 64-bit process, an internal indicator is set to indicate the application process as either a 32-bit process or a 64-bit process. Subsequently, the internal indicator is identified as either indicating the 32-bit process or the 64-bit process. If the internal identifier indicates the application process is a 32-bit process, an instruction pointer is set to indicate the 32-bit trace executable code, and the 32-bit trace executable code is executed. If the internal identifier indicates the application process is a 64-bit process, an instruction pointer is set to indicate the 64-bit trace executable code, and the 64-bit trace executable code is executed.

Selective execution of trace mechanisms for applications having different bit structures

A SMT enabled processor system, having multiple processors each activated to interleave execution of multiple hardware threads on each processor, for ST workload, includes a kernel. The kernel of the SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. The ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually removing the remaining idle hardware threads per processor within the exclusive set of processors.

A data processing system allows processes to be checkpointed and restarted. The system saves the old process and thread identifications in a process table. When an application makes a system call passing the old process and/or thread identifications as parameters, the system performs a mapping algorithm to supply the system call with the new process and/or thread identifications. When a system call returns a new identification, the system performs a remapping algorithm to return the old identifications to the calling application program. When a group of process is restarted for which the process group leader was not checkpointed, the system creates a ghost process group leader.

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Austin, TX, United States of America

Suresh Eswara Warrier