Intel Corporation

Inter Corporation

Suresh Chemudupati

Victor Lau

Ankush Varma

Pak-Lung Seto

William R Halleck

Adwait Purandare

Krishnakanth Venkata Sistla

Andrew J Herdrich

Alexander Gendler

Vivek Garg

Dean A Mulla

Eric J DeHaemer

Bharat S Pillilli

Nikhil Gupta

Gary Tsao

Nai-Chih Chang

Nazar Syed Haider

Phani Kumar Kandula

Naichih Chang

Ripan Das

David Hunt

Yogesh Bansal

Yi-Feng Liu

Aman Sewani

Eric Dehaemer

Nilanjan Palit

Rupal Parikh

Ujjwal Gupta

Pavithra Sampath

Nikethan Shivanand Baligar

Stanley Chen

Kiran Vemula

Ankit Parikh

Bruno DiPlacido

Pritesh P Shah

Christopher M Macnamara

Ofer Nathan

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

Hardware-assisted core frequency and voltage scaling in a poll mode idle loop

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.

Configurable flush of data from volatile memory to non-volatile memory

A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.

Parallel processing of frame based data transfers

A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.

Centralized error signaling and logging

According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.

DMA completion processing mechanism

Growing community of inventors

Marlborough, MA, United States of America

Suresh Chemudupati