Vishay-siliconix

Fairchild Semiconductor Corporation

Suresh Belani

Frank Kuo

Steven Paul Sapp

Chung-Lin Wu

Bigildis Dosdos

Sunggeun Yoon

Sen Mao

Serge Jaunay

Peter Wang

A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Dual lead frame semiconductor package and method of manufacture

A first embodiment is a common drain+clip. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframewhich has external source, gate and drain contacts connected to the sources, gate and common drain of the die. Common drain clipconnects the drainto external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The devicehas a top drain contactthat extends to the common drainacross the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die

Common drain power clip for battery pack protection mosfet

The multi-chip leadless modulehas integrated circuit (IC), dual n-channel mosfet, IC leads, gate leads, and source leads-encapsulated in resin. The ICand the dual n-channel mosfetare mounted face down on the leads. IC leadsare made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the ICusing a flip chip technique to assemble the leads on copper pillars or copper studs.

Multi-chip module power clip

The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Growing community of inventors

Los Altos, CA, United States of America

Suresh Belani