Apple Inc.

Suresh Balasubramanian

Ajay Bhatia

Vivekanandan Venugopal

Suparn Vats

Raghava Rao V Denduluri

Gopinath Venkatesh

Teng Wang

Erick Omar Torres

Khaled M Alashmouny

Sunil Bhosekar

Bruce Andrew Doyle

Sharath R Srinivasan

Chad O Lackey

An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Hybrid pulse/two-stage data latch

Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

Clock duty cycle correction

Hybrid pulse/master-slave data latch

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Cupertino, CA, United States of America

Suresh Balasubramanian