Cavium, Inc.

Intel Corporation

Suresh Balasubramanian

David Lin

Georgios Faldamis

Steve Aiken

Maurice B Steinman

Tim Frodsham

Warren Anderson

Christopher C Gianos

Nitin Mohan

Manan Salvi

Horst W Wagner

Richard M Watson

Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal; at a first leaf node of the clock distribution network, detecting a reference event and generating a synchronizing signal based on the detection of the reference event; passing the synchronizing signal along a synchronizing signal path from the first leaf node to the root node via one or more clocked storage cells, each storage cell being clocked from a corresponding point within the clock distribution network; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal received at the root node, and distributing the second clock signal to the leaf nodes of the clock distribution network, the generating of the second clock signal resulting in the second clock signal received at the first leaf node being synchronized to the detected reference event.

Frequency division clock alignment

Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal.

Frequency division clock alignment using pattern selection

In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal.

Clock distribution circuit with distributed delay locked loop

A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.

Multi-function delay locked loop

In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.

Scannable flop with a single storage element

In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.

Multiplexer flop

In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value.

Clock gated delay line based on setting value

A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.

State machine for deskew delay locked loop

In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.

Growing community of inventors

Shrewsbury, MA, United States of America

Suresh Balasubramanian